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[Qemu-riscv] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT |
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Date: |
Thu, 15 Nov 2018 22:34:56 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 45 ++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index e5eca4bbbe..a9c57493a0 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -118,3 +118,48 @@ static const int tcg_target_call_oarg_regs[] = {
#define TCG_CT_CONST_ZERO 0x100
#define TCG_CT_CONST_S12 0x200
#define TCG_CT_CONST_N12 0x400
+
+typedef struct {
+ DebugFrameHeader h;
+ uint8_t fde_def_cfa[4];
+ uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
+} DebugFrame;
+
+#define ELF_HOST_MACHINE EM_RISCV
+
+static const DebugFrame debug_frame = {
+ .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
+ .h.cie.id = -1,
+ .h.cie.version = 1,
+ .h.cie.code_align = 1,
+ .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
+ .h.cie.return_column = TCG_REG_RA,
+
+ /* Total FDE size does not include the "len" member. */
+ .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+ .fde_def_cfa = {
+ 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
+ (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+ (FRAME_SIZE >> 7)
+ },
+ .fde_reg_ofs = {
+ 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */
+ 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */
+ 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */
+ 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */
+ 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */
+ 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */
+ 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */
+ 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */
+ 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */
+ 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */
+ 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */
+ 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */
+ }
+};
+
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+ tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
+}
--
2.19.1
- Re: [Qemu-riscv] [Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit, (continued)
- [Qemu-riscv] [RFC v1 03/23] linux-user: Add host dependency for RISC-V 64-bit, Alistair Francis, 2018/11/15
- [Qemu-riscv] [RFC v1 04/23] exec: Add RISC-V GCC poison macro, Alistair Francis, 2018/11/15
- [Qemu-riscv] [RFC v1 05/23] riscv: Add the tcg-target header file, Alistair Francis, 2018/11/15
- [Qemu-riscv] [RFC v1 06/23] riscv: Add the tcg target registers, Alistair Francis, 2018/11/15
- [Qemu-riscv] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT,
Alistair Francis <=
- [Qemu-riscv] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/11/15
- [Qemu-riscv] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/11/15
- [Qemu-riscv] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/11/15