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Re: [Qemu-riscv] [Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add supp
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-riscv] [Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints |
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Date: |
Fri, 16 Nov 2018 09:13:38 +0100 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.0 |
On 11/15/18 11:35 PM, Alistair Francis wrote:
> + case 'L':
> + /* qemu_ld/qemu_st constraint */
> + ct->ct |= TCG_CT_REG;
> + ct->u.regs = 0xffffffff;
> + /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
> +#if defined(CONFIG_SOFTMMU)
> + /* tcg_out_tlb_load uses TCG_REG_TMP0/TMP1 and TCG_REG_L0/L1 */
> + /* tcg_regset_reset_reg(ct->u.regs, TCG_REG_TMP0); */
> + /* tcg_regset_reset_reg(ct->u.regs, TCG_REG_TMP1); */
> + tcg_regset_reset_reg(ct->u.regs, TCG_REG_TMP2);
Normally TMP registers are reserved and do not need to be mentioned in
constraints at all.
> + if ((ct & TCG_CT_CONST_S12) && val >= -2048 && val <= 2047) {
> + return 1;
> + }
> + if ((ct & TCG_CT_CONST_N12) && val >= -2047 && val <= 2048) {
> + return 1;
> + }
Clearer as val == sextracttl(val, 0, 12)
and -val == sextracttl(-val, 0, 12)?
r~
- [Qemu-riscv] [RFC v1 04/23] exec: Add RISC-V GCC poison macro, (continued)
- [Qemu-riscv] [RFC v1 04/23] exec: Add RISC-V GCC poison macro, Alistair Francis, 2018/11/15
- [Qemu-riscv] [RFC v1 05/23] riscv: Add the tcg-target header file, Alistair Francis, 2018/11/15
- [Qemu-riscv] [RFC v1 06/23] riscv: Add the tcg target registers, Alistair Francis, 2018/11/15
- [Qemu-riscv] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT, Alistair Francis, 2018/11/15
- [Qemu-riscv] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/11/15
- Re: [Qemu-riscv] [Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints,
Richard Henderson <=
- [Qemu-riscv] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/11/15
- [Qemu-riscv] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/11/15
[Qemu-riscv] [RFC v1 10/23] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/11/15