[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 26/38] target/riscv: Disable guest FP support based on virtual sta
|
From: |
Palmer Dabbelt |
|
Subject: |
[PULL 26/38] target/riscv: Disable guest FP support based on virtual status |
|
Date: |
Mon, 2 Mar 2020 16:48:36 -0800 |
From: Alistair Francis <address@hidden>
When the Hypervisor extension is in use we only enable floating point
support when both status and vsstatus have enabled floating point
support.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 895b6ca25d..d9a29d702a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -99,6 +99,9 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
bool riscv_cpu_fp_enabled(CPURISCVState *env)
{
if (env->mstatus & MSTATUS_FS) {
+ if (riscv_cpu_virt_enabled(env) && !(env->mstatus_hs & MSTATUS_FS)) {
+ return false;
+ }
return true;
}
--
2.25.0.265.gbab2e86ba0-goog
- [PULL 22/38] target/riscv: Add Hypervisor trap return support, (continued)
- [PULL 22/38] target/riscv: Add Hypervisor trap return support, Palmer Dabbelt, 2020/03/02
- [PULL 31/38] target/riscv: Raise the new execptions when 2nd stage translation fails, Palmer Dabbelt, 2020/03/02
- [PULL 30/38] target/riscv: Implement second stage MMU, Palmer Dabbelt, 2020/03/02
- [PULL 19/38] target/ricsv: Flush the TLB on virtulisation mode changes, Palmer Dabbelt, 2020/03/02
- [PULL 23/38] target/riscv: Add hfence instructions, Palmer Dabbelt, 2020/03/02
- [PULL 20/38] target/riscv: Generate illegal instruction on WFI when V=1, Palmer Dabbelt, 2020/03/02
- [PULL 24/38] target/riscv: Remove the hret instruction, Palmer Dabbelt, 2020/03/02
- [PULL 33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR, Palmer Dabbelt, 2020/03/02
- [PULL 29/38] target/riscv: Allow specifying MMU stage, Palmer Dabbelt, 2020/03/02
- [PULL 25/38] target/riscv: Only set TB flags with FP status if enabled, Palmer Dabbelt, 2020/03/02
- [PULL 26/38] target/riscv: Disable guest FP support based on virtual status,
Palmer Dabbelt <=
- [PULL 27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty, Palmer Dabbelt, 2020/03/02
- [PULL 28/38] target/riscv: Respect MPRV and SPRV for floating point ops, Palmer Dabbelt, 2020/03/02
- [PULL 34/38] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Palmer Dabbelt, 2020/03/02
- [PULL 35/38] target/riscv: Allow enabling the Hypervisor extension, Palmer Dabbelt, 2020/03/02
- [PULL 38/38] hw/riscv: Provide rdtime callback for TCG in CLINT emulation, Palmer Dabbelt, 2020/03/02
- [PULL 36/38] riscv: virt: Allow PCI address 0, Palmer Dabbelt, 2020/03/02
- [PULL 37/38] target/riscv: Emulate TIME CSRs for privileged mode, Palmer Dabbelt, 2020/03/02
- [PULL 32/38] target/riscv: Set htval and mtval2 on execptions, Palmer Dabbelt, 2020/03/02
- Re: [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3, Peter Maydell, 2020/03/03