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[PULL 29/38] target/riscv: Allow specifying MMU stage
From: |
Palmer Dabbelt |
Subject: |
[PULL 29/38] target/riscv: Allow specifying MMU stage |
Date: |
Mon, 2 Mar 2020 16:48:39 -0800 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu_helper.c | 37 ++++++++++++++++++++++++++++---------
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d9a29d702a..8ae1038bcd 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -277,10 +277,19 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulong
newpriv)
*
* Adapted from Spike's mmu_t::translate and mmu_t::walk
*
+ * @env: CPURISCVState
+ * @physical: This will be set to the calculated physical address
+ * @prot: The returned protection attributes
+ * @addr: The virtual address to be translated
+ * @access_type: The type of MMU access
+ * @mmu_idx: Indicates current privilege level
+ * @first_stage: Are we in first stage translation?
+ * Second stage is used for hypervisor guest translation
*/
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
int *prot, target_ulong addr,
- int access_type, int mmu_idx)
+ int access_type, int mmu_idx,
+ bool first_stage)
{
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
@@ -485,13 +494,21 @@ restart:
}
static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
- MMUAccessType access_type, bool pmp_violation)
+ MMUAccessType access_type, bool pmp_violation,
+ bool first_stage)
{
CPUState *cs = env_cpu(env);
- int page_fault_exceptions =
- (env->priv_ver >= PRIV_VERSION_1_10_0) &&
- get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
- !pmp_violation;
+ int page_fault_exceptions;
+ if (first_stage) {
+ page_fault_exceptions =
+ (env->priv_ver >= PRIV_VERSION_1_10_0) &&
+ get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
+ !pmp_violation;
+ } else {
+ page_fault_exceptions =
+ get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
+ !pmp_violation;
+ }
switch (access_type) {
case MMU_INST_FETCH:
cs->exception_index = page_fault_exceptions ?
@@ -518,7 +535,8 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr
addr)
int prot;
int mmu_idx = cpu_mmu_index(&cpu->env, false);
- if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) {
+ if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx,
+ true)) {
return -1;
}
return phys_addr;
@@ -583,7 +601,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, address, access_type, mmu_idx);
- ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx);
+ ret = get_physical_address(env, &pa, &prot, address, access_type, mmu_idx,
+ true);
if (mode == PRV_M && access_type != MMU_INST_FETCH) {
if (get_field(env->mstatus, MSTATUS_MPRV)) {
@@ -610,7 +629,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
} else if (probe) {
return false;
} else {
- raise_mmu_exception(env, address, access_type, pmp_violation);
+ raise_mmu_exception(env, address, access_type, pmp_violation, true);
riscv_raise_exception(env, cs->exception_index, retaddr);
}
#else
--
2.25.0.265.gbab2e86ba0-goog
- [PULL 18/38] target/riscv: Add support for virtual interrupt setting, (continued)
- [PULL 18/38] target/riscv: Add support for virtual interrupt setting, Palmer Dabbelt, 2020/03/02
- [PULL 13/38] target/riscv: Add Hypervisor machine CSRs accesses, Palmer Dabbelt, 2020/03/02
- [PULL 22/38] target/riscv: Add Hypervisor trap return support, Palmer Dabbelt, 2020/03/02
- [PULL 31/38] target/riscv: Raise the new execptions when 2nd stage translation fails, Palmer Dabbelt, 2020/03/02
- [PULL 30/38] target/riscv: Implement second stage MMU, Palmer Dabbelt, 2020/03/02
- [PULL 19/38] target/ricsv: Flush the TLB on virtulisation mode changes, Palmer Dabbelt, 2020/03/02
- [PULL 23/38] target/riscv: Add hfence instructions, Palmer Dabbelt, 2020/03/02
- [PULL 20/38] target/riscv: Generate illegal instruction on WFI when V=1, Palmer Dabbelt, 2020/03/02
- [PULL 24/38] target/riscv: Remove the hret instruction, Palmer Dabbelt, 2020/03/02
- [PULL 33/38] target/riscv: Add support for the 32-bit MSTATUSH CSR, Palmer Dabbelt, 2020/03/02
- [PULL 29/38] target/riscv: Allow specifying MMU stage,
Palmer Dabbelt <=
- [PULL 25/38] target/riscv: Only set TB flags with FP status if enabled, Palmer Dabbelt, 2020/03/02
- [PULL 26/38] target/riscv: Disable guest FP support based on virtual status, Palmer Dabbelt, 2020/03/02
- [PULL 27/38] target/riscv: Mark both sstatus and msstatus_hs as dirty, Palmer Dabbelt, 2020/03/02
- [PULL 28/38] target/riscv: Respect MPRV and SPRV for floating point ops, Palmer Dabbelt, 2020/03/02
- [PULL 34/38] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Palmer Dabbelt, 2020/03/02
- [PULL 35/38] target/riscv: Allow enabling the Hypervisor extension, Palmer Dabbelt, 2020/03/02
- [PULL 38/38] hw/riscv: Provide rdtime callback for TCG in CLINT emulation, Palmer Dabbelt, 2020/03/02
- [PULL 36/38] riscv: virt: Allow PCI address 0, Palmer Dabbelt, 2020/03/02
- [PULL 37/38] target/riscv: Emulate TIME CSRs for privileged mode, Palmer Dabbelt, 2020/03/02
- [PULL 32/38] target/riscv: Set htval and mtval2 on execptions, Palmer Dabbelt, 2020/03/02