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Re: [PULL 04/38] target/riscv: Add support for the new execption numbers
From: |
Alistair Francis |
Subject: |
Re: [PULL 04/38] target/riscv: Add support for the new execption numbers |
Date: |
Thu, 5 Mar 2020 08:46:47 -0800 |
On Thu, Mar 5, 2020 at 8:52 AM Peter Maydell <address@hidden> wrote:
>
> On Tue, 3 Mar 2020 at 00:49, Palmer Dabbelt <address@hidden> wrote:
> >
> > From: Alistair Francis <address@hidden>
> >
> > The v0.5 Hypervisor spec add new execption numbers, let's add support
> > for those.
> >
> > Signed-off-by: Alistair Francis <address@hidden>
> > Reviewed-by: Palmer Dabbelt <address@hidden>
> > Signed-off-by: Palmer Dabbelt <address@hidden>
> > ---
> > target/riscv/cpu.c | 8 ++++++++
> > target/riscv/cpu_bits.h | 35 +++++++++++++++++++----------------
> > target/riscv/cpu_helper.c | 7 +++++--
> > target/riscv/csr.c | 7 +++++--
> > 4 files changed, 37 insertions(+), 20 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index efbd676edb..2f62f5ea19 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -67,6 +67,14 @@ const char * const riscv_excp_names[] = {
> > "load_page_fault",
> > "reserved",
> > "store_page_fault"
> > + "reserved",
>
> Hi; Coverity (CID 1420223) notice that there's no comma
> after "store_page_fault", which means that there's been
> a concatenation of that string and the following "reserved".
> Could one of you send a patch which adds the missing comma?
>
> > + "reserved",
> > + "reserved",
> > + "reserved",
> > + "guest_exec_page_fault",
> > + "guest_load_page_fault",
> > + "reserved",
> > + "guest_store_page_fault"
>
> You might also like to add a trailing comma here to avoid
> the bug happening again in future.
Thanks for the report Peter, I'll send a patch.
Alistair
>
> > };
> >
>
> thanks
> -- PMM
>
- [PULL 11/38] target/riscv: Add Hypervisor CSR access functions, (continued)
- [PULL 11/38] target/riscv: Add Hypervisor CSR access functions, Palmer Dabbelt, 2020/03/02
- [PULL 09/38] target/riscv: Print priv and virt in disas log, Palmer Dabbelt, 2020/03/02
- [PULL 06/38] target/riscv: Add the virtulisation mode, Palmer Dabbelt, 2020/03/02
- [PULL 07/38] target/riscv: Add the force HS exception mode, Palmer Dabbelt, 2020/03/02
- [PULL 14/38] target/riscv: Add virtual register swapping function, Palmer Dabbelt, 2020/03/02
- [PULL 17/38] target/riscv: Extend the SIP CSR to support virtulisation, Palmer Dabbelt, 2020/03/02
- [PULL 21/38] target/riscv: Add hypvervisor trap support, Palmer Dabbelt, 2020/03/02
- [PULL 04/38] target/riscv: Add support for the new execption numbers, Palmer Dabbelt, 2020/03/02
- [PULL 15/38] target/riscv: Set VS bits in mideleg for Hyp extension, Palmer Dabbelt, 2020/03/02
- [PULL 16/38] target/riscv: Extend the MIE CSR to support virtulisation, Palmer Dabbelt, 2020/03/02
- [PULL 10/38] target/riscv: Dump Hypervisor registers if enabled, Palmer Dabbelt, 2020/03/02
- [PULL 12/38] target/riscv: Add Hypervisor virtual CSRs accesses, Palmer Dabbelt, 2020/03/02
- [PULL 18/38] target/riscv: Add support for virtual interrupt setting, Palmer Dabbelt, 2020/03/02
- [PULL 13/38] target/riscv: Add Hypervisor machine CSRs accesses, Palmer Dabbelt, 2020/03/02
- [PULL 22/38] target/riscv: Add Hypervisor trap return support, Palmer Dabbelt, 2020/03/02
- [PULL 31/38] target/riscv: Raise the new execptions when 2nd stage translation fails, Palmer Dabbelt, 2020/03/02
- [PULL 30/38] target/riscv: Implement second stage MMU, Palmer Dabbelt, 2020/03/02
- [PULL 19/38] target/ricsv: Flush the TLB on virtulisation mode changes, Palmer Dabbelt, 2020/03/02