Re: [PATCH v6 19/61] target/riscv: vector integer divide instructions

qemu-riscv

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v6 19/61] target/riscv: vector integer divide instructions

From:	Alistair Francis
Subject:	Re: [PATCH v6 19/61] target/riscv: vector integer divide instructions
Date:	Fri, 20 Mar 2020 11:51:19 -0700

On Tue, Mar 17, 2020 at 8:45 AM LIU Zhiwei <address@hidden> wrote:
>
> Signed-off-by: LIU Zhiwei <address@hidden>
> Reviewed-by: Richard Henderson <address@hidden>

Reviewed-by: Alistair Francis <address@hidden>

Alistair

> ---
>  target/riscv/helper.h                   | 33 +++++++++++
>  target/riscv/insn32.decode              |  8 +++
>  target/riscv/insn_trans/trans_rvv.inc.c | 10 ++++
>  target/riscv/vector_helper.c            | 74 +++++++++++++++++++++++++
>  4 files changed, 125 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index f42a12eef3..357f149198 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -558,3 +558,36 @@ DEF_HELPER_6(vmulhsu_vx_b, void, ptr, ptr, tl, ptr, env, 
> i32)
>  DEF_HELPER_6(vmulhsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vmulhsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vmulhsu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
> +
> +DEF_HELPER_6(vdivu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vdivu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vdivu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vdivu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vdiv_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vdiv_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vdiv_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vdiv_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vremu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vremu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vremu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vremu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vrem_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vrem_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vrem_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vrem_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vdivu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vdivu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vdivu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vdivu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vdiv_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vdiv_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vdiv_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vdiv_vx_d, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vremu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vremu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vremu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vremu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vrem_vx_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vrem_vx_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vrem_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vrem_vx_d, void, ptr, ptr, tl, ptr, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index abfed469bc..7fb8f8fad8 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -371,6 +371,14 @@ vmulhu_vv       100100 . ..... ..... 010 ..... 1010111 
> @r_vm
>  vmulhu_vx       100100 . ..... ..... 110 ..... 1010111 @r_vm
>  vmulhsu_vv      100110 . ..... ..... 010 ..... 1010111 @r_vm
>  vmulhsu_vx      100110 . ..... ..... 110 ..... 1010111 @r_vm
> +vdivu_vv        100000 . ..... ..... 010 ..... 1010111 @r_vm
> +vdivu_vx        100000 . ..... ..... 110 ..... 1010111 @r_vm
> +vdiv_vv         100001 . ..... ..... 010 ..... 1010111 @r_vm
> +vdiv_vx         100001 . ..... ..... 110 ..... 1010111 @r_vm
> +vremu_vv        100010 . ..... ..... 010 ..... 1010111 @r_vm
> +vremu_vx        100010 . ..... ..... 110 ..... 1010111 @r_vm
> +vrem_vv         100011 . ..... ..... 010 ..... 1010111 @r_vm
> +vrem_vx         100011 . ..... ..... 110 ..... 1010111 @r_vm
>
>  vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
>  vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
> b/target/riscv/insn_trans/trans_rvv.inc.c
> index c276beabd6..ed53eaaef5 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -1462,3 +1462,13 @@ GEN_OPIVX_GVEC_TRANS(vmul_vx,  muls)
>  GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
>  GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
>  GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
> +
> +/* Vector Integer Divide Instructions */
> +GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
> +GEN_OPIVV_TRANS(vdiv_vv, opivv_check)
> +GEN_OPIVV_TRANS(vremu_vv, opivv_check)
> +GEN_OPIVV_TRANS(vrem_vv, opivv_check)
> +GEN_OPIVX_TRANS(vdivu_vx, opivx_check)
> +GEN_OPIVX_TRANS(vdiv_vx, opivx_check)
> +GEN_OPIVX_TRANS(vremu_vx, opivx_check)
> +GEN_OPIVX_TRANS(vrem_vx, opivx_check)
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 56ba9a7422..4fc7a08954 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -1741,3 +1741,77 @@ GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb)
>  GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh)
>  GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl)
>  GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq)
> +
> +/* Vector Integer Divide Instructions */
> +#define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
> +#define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M)
> +#define DO_DIV(N, M)  (unlikely(M == 0) ? (__typeof(N))(-1) :\
> +        unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
> +#define DO_REM(N, M)  (unlikely(M == 0) ? N :\
> +        unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
> +
> +RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU)
> +RVVCALL(OPIVV2, vdivu_vv_h, OP_UUU_H, H2, H2, H2, DO_DIVU)
> +RVVCALL(OPIVV2, vdivu_vv_w, OP_UUU_W, H4, H4, H4, DO_DIVU)
> +RVVCALL(OPIVV2, vdivu_vv_d, OP_UUU_D, H8, H8, H8, DO_DIVU)
> +RVVCALL(OPIVV2, vdiv_vv_b, OP_SSS_B, H1, H1, H1, DO_DIV)
> +RVVCALL(OPIVV2, vdiv_vv_h, OP_SSS_H, H2, H2, H2, DO_DIV)
> +RVVCALL(OPIVV2, vdiv_vv_w, OP_SSS_W, H4, H4, H4, DO_DIV)
> +RVVCALL(OPIVV2, vdiv_vv_d, OP_SSS_D, H8, H8, H8, DO_DIV)
> +RVVCALL(OPIVV2, vremu_vv_b, OP_UUU_B, H1, H1, H1, DO_REMU)
> +RVVCALL(OPIVV2, vremu_vv_h, OP_UUU_H, H2, H2, H2, DO_REMU)
> +RVVCALL(OPIVV2, vremu_vv_w, OP_UUU_W, H4, H4, H4, DO_REMU)
> +RVVCALL(OPIVV2, vremu_vv_d, OP_UUU_D, H8, H8, H8, DO_REMU)
> +RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM)
> +RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM)
> +RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM)
> +RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM)
> +GEN_VEXT_VV(vdivu_vv_b, 1, 1, clearb)
> +GEN_VEXT_VV(vdivu_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV(vdivu_vv_w, 4, 4, clearl)
> +GEN_VEXT_VV(vdivu_vv_d, 8, 8, clearq)
> +GEN_VEXT_VV(vdiv_vv_b, 1, 1, clearb)
> +GEN_VEXT_VV(vdiv_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV(vdiv_vv_w, 4, 4, clearl)
> +GEN_VEXT_VV(vdiv_vv_d, 8, 8, clearq)
> +GEN_VEXT_VV(vremu_vv_b, 1, 1, clearb)
> +GEN_VEXT_VV(vremu_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV(vremu_vv_w, 4, 4, clearl)
> +GEN_VEXT_VV(vremu_vv_d, 8, 8, clearq)
> +GEN_VEXT_VV(vrem_vv_b, 1, 1, clearb)
> +GEN_VEXT_VV(vrem_vv_h, 2, 2, clearh)
> +GEN_VEXT_VV(vrem_vv_w, 4, 4, clearl)
> +GEN_VEXT_VV(vrem_vv_d, 8, 8, clearq)
> +
> +RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU)
> +RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU)
> +RVVCALL(OPIVX2, vdivu_vx_w, OP_UUU_W, H4, H4, DO_DIVU)
> +RVVCALL(OPIVX2, vdivu_vx_d, OP_UUU_D, H8, H8, DO_DIVU)
> +RVVCALL(OPIVX2, vdiv_vx_b, OP_SSS_B, H1, H1, DO_DIV)
> +RVVCALL(OPIVX2, vdiv_vx_h, OP_SSS_H, H2, H2, DO_DIV)
> +RVVCALL(OPIVX2, vdiv_vx_w, OP_SSS_W, H4, H4, DO_DIV)
> +RVVCALL(OPIVX2, vdiv_vx_d, OP_SSS_D, H8, H8, DO_DIV)
> +RVVCALL(OPIVX2, vremu_vx_b, OP_UUU_B, H1, H1, DO_REMU)
> +RVVCALL(OPIVX2, vremu_vx_h, OP_UUU_H, H2, H2, DO_REMU)
> +RVVCALL(OPIVX2, vremu_vx_w, OP_UUU_W, H4, H4, DO_REMU)
> +RVVCALL(OPIVX2, vremu_vx_d, OP_UUU_D, H8, H8, DO_REMU)
> +RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM)
> +RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM)
> +RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM)
> +RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM)
> +GEN_VEXT_VX(vdivu_vx_b, 1, 1, clearb)
> +GEN_VEXT_VX(vdivu_vx_h, 2, 2, clearh)
> +GEN_VEXT_VX(vdivu_vx_w, 4, 4, clearl)
> +GEN_VEXT_VX(vdivu_vx_d, 8, 8, clearq)
> +GEN_VEXT_VX(vdiv_vx_b, 1, 1, clearb)
> +GEN_VEXT_VX(vdiv_vx_h, 2, 2, clearh)
> +GEN_VEXT_VX(vdiv_vx_w, 4, 4, clearl)
> +GEN_VEXT_VX(vdiv_vx_d, 8, 8, clearq)
> +GEN_VEXT_VX(vremu_vx_b, 1, 1, clearb)
> +GEN_VEXT_VX(vremu_vx_h, 2, 2, clearh)
> +GEN_VEXT_VX(vremu_vx_w, 4, 4, clearl)
> +GEN_VEXT_VX(vremu_vx_d, 8, 8, clearq)
> +GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb)
> +GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh)
> +GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl)
> +GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq)
> --
> 2.23.0
>

[Prev in Thread]

Current Thread

[Next in Thread]

[PATCH v6 17/61] target/riscv: vector integer min/max instructions, (continued)
- [PATCH v6 17/61] target/riscv: vector integer min/max instructions, LIU Zhiwei, 2020/03/17
  - Re: [PATCH v6 17/61] target/riscv: vector integer min/max instructions, Alistair Francis, 2020/03/20
- [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions, LIU Zhiwei, 2020/03/17
  - Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions, Alistair Francis, 2020/03/25
  - Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions, Richard Henderson, 2020/03/27
    - Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions, LIU Zhiwei, 2020/03/28
    - Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions, Richard Henderson, 2020/03/28
    - Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions, LIU Zhiwei, 2020/03/28
    - Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions, LIU Zhiwei, 2020/03/29
- [PATCH v6 19/61] target/riscv: vector integer divide instructions, LIU Zhiwei, 2020/03/17
  - Re: [PATCH v6 19/61] target/riscv: vector integer divide instructions, Alistair Francis <=
- [PATCH v6 20/61] target/riscv: vector widening integer multiply instructions, LIU Zhiwei, 2020/03/17
  - Re: [PATCH v6 20/61] target/riscv: vector widening integer multiply instructions, Alistair Francis, 2020/03/25
- [PATCH v6 21/61] target/riscv: vector single-width integer multiply-add instructions, LIU Zhiwei, 2020/03/17
  - Re: [PATCH v6 21/61] target/riscv: vector single-width integer multiply-add instructions, Alistair Francis, 2020/03/25
- [PATCH v6 22/61] target/riscv: vector widening integer multiply-add instructions, LIU Zhiwei, 2020/03/17
  - Re: [PATCH v6 22/61] target/riscv: vector widening integer multiply-add instructions, Alistair Francis, 2020/03/25
- [PATCH v6 23/61] target/riscv: vector integer merge and move instructions, LIU Zhiwei, 2020/03/17
  - Re: [PATCH v6 23/61] target/riscv: vector integer merge and move instructions, Alistair Francis, 2020/03/26
  - Re: [PATCH v6 23/61] target/riscv: vector integer merge and move instructions, Richard Henderson, 2020/03/27
- [PATCH v6 24/61] target/riscv: vector single-width saturating add and subtract, LIU Zhiwei, 2020/03/17

Prev by Date: Re: [PATCH v6 17/61] target/riscv: vector integer min/max instructions
Next by Date: Re: [PATCH v6 04/61] target/riscv: add vector configure instruction
Previous by thread: [PATCH v6 19/61] target/riscv: vector integer divide instructions
Next by thread: [PATCH v6 20/61] target/riscv: vector widening integer multiply instructions
Index(es):
- Date
- Thread