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Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply


From: LIU Zhiwei
Subject: Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions
Date: Sat, 28 Mar 2020 23:17:11 +0800
User-agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0



On 2020/3/28 8:06, Richard Henderson wrote:
On 3/17/20 8:06 AM, LIU Zhiwei wrote:
+static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
+{
+    uint64_t hi_64, lo_64, abs_s2 = s2;
+
+    if (s2 < 0) {
+        abs_s2 = -s2;
+    }
+    mulu64(&lo_64, &hi_64, abs_s2, s1);
+    if (s2 < 0) {
+        lo_64 = ~lo_64;
+        hi_64 = ~hi_64;
+        if (lo_64 == UINT64_MAX) {
+            lo_64 = 0;
+            hi_64 += 1;
+        } else {
+            lo_64 += 1;
+        }
+    }
+
+    return hi_64;
+}
Missed the improvement here.  See tcg_gen_mulsu2_i64.
Though I have not gotten the principle, the code in tcg_gen_mulsu2_i64 is much tidier.

Thanks for pointing that.

Zhiwei
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>


r~




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