[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v6 55/61] target/riscv: integer extract instruction
|
From: |
Richard Henderson |
|
Subject: |
Re: [PATCH v6 55/61] target/riscv: integer extract instruction |
|
Date: |
Fri, 27 Mar 2020 20:36:37 -0700 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/17/20 8:06 AM, LIU Zhiwei wrote:
> +/* Integer Extract Instruction */
> +static void extract_element(TCGv dest, TCGv_ptr base,
> + int ofs, int sew)
> +{
> + switch (sew) {
> + case MO_8:
> + tcg_gen_ld8u_tl(dest, base, ofs);
> + break;
> + case MO_16:
> + tcg_gen_ld16u_tl(dest, base, ofs);
> + break;
> + default:
> + tcg_gen_ld32u_tl(dest, base, ofs);
> + break;
> +#if TARGET_LONG_BITS == 64
> + case MO_64:
> + tcg_gen_ld_i64(dest, base, ofs);
> + break;
> +#endif
> + }
> +}
I just remembered that this doesn't handle HOST_WORDS_BIGENDIAN properly -- the
MO_64 case for TARGET_LONG_BITS == 32.
Because we computed the offset for MO_64, not MO_32, we need
case MO_64:
if (TARGET_LONG_BITS == 64) {
tcg_gen_ld_i64(dest, base, ofs);
break;
}
#ifdef HOST_WORDS_BIGENDIAN
ofs += 4;
#endif
/* fall through */
case MO_32:
tcg_gen_ld32u_tl(dest, base, ofs);
break;
default:
g_assert_not_reached();
r~
- [PATCH v6 46/61] target/riscv: vector wideing integer reduction instructions, (continued)
- [PATCH v6 46/61] target/riscv: vector wideing integer reduction instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 47/61] target/riscv: vector single-width floating-point reduction instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 48/61] target/riscv: vector widening floating-point reduction instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 49/61] target/riscv: vector mask-register logical instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 50/61] target/riscv: vector mask population count vmpopc, LIU Zhiwei, 2020/03/17
- [PATCH v6 51/61] target/riscv: vmfirst find-first-set mask bit, LIU Zhiwei, 2020/03/17
- [PATCH v6 52/61] target/riscv: set-X-first mask bit, LIU Zhiwei, 2020/03/17
- [PATCH v6 53/61] target/riscv: vector iota instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 54/61] target/riscv: vector element index instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 55/61] target/riscv: integer extract instruction, LIU Zhiwei, 2020/03/17
- Re: [PATCH v6 55/61] target/riscv: integer extract instruction,
Richard Henderson <=
- [PATCH v6 56/61] target/riscv: integer scalar move instruction, LIU Zhiwei, 2020/03/17
- [PATCH v6 57/61] target/riscv: floating-point scalar move instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 58/61] target/riscv: vector slide instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 59/61] target/riscv: vector register gather instruction, LIU Zhiwei, 2020/03/17