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[RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from
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From: |
frank . chang |
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Subject: |
[RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register |
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Date: |
Wed, 22 Jul 2020 17:15:34 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Remove VXRM and VXSAT fields from FCSR register
as they are only presented in VCSR register.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/csr.c | 8 --------
1 file changed, 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ab4a4fc132..33c77be06e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -166,10 +166,6 @@ static int read_fcsr(CPURISCVState *env, int csrno,
target_ulong *val)
#endif
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
- if (vs(env, csrno) >= 0) {
- *val |= (env->vxrm << FSR_VXRM_SHIFT)
- | (env->vxsat << FSR_VXSAT_SHIFT);
- }
return 0;
}
@@ -183,10 +179,6 @@ static int write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
env->mstatus |= MSTATUS_VS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
- if (vs(env, csrno) >= 0) {
- env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
- env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
- }
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
return 0;
}
--
2.17.1
- [RFC v2 05/76] target/riscv: fix return value of do_opivx_widen(), (continued)
- [RFC v2 05/76] target/riscv: fix return value of do_opivx_widen(), frank . chang, 2020/07/22
- [RFC v2 06/76] target/riscv: fix vill bit index in vtype register, frank . chang, 2020/07/22
- [RFC v2 07/76] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2020/07/22
- [RFC v2 08/76] target/riscv: rvv-0.9: add mstatus VS field, frank . chang, 2020/07/22
- [RFC v2 09/76] target/riscv: rvv-0.9: add sstatus VS field, frank . chang, 2020/07/22
- [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status, frank . chang, 2020/07/22
- [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register,
frank . chang <=
- [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/22
- [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register, frank . chang, 2020/07/22
- [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations, frank . chang, 2020/07/22
- [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL, frank . chang, 2020/07/22