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Re: [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL
From: |
Richard Henderson |
Subject: |
Re: [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL |
Date: |
Wed, 22 Jul 2020 10:30:44 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 7/22/20 2:15 AM, frank.chang@sifive.com wrote:
> FIELD(VTYPE, VLMUL, 0, 2)
> FIELD(VTYPE, VSEW, 2, 3)
> -FIELD(VTYPE, VEDIV, 5, 2)
> -FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
> +FIELD(VTYPE, VFLMUL, 5, 1)
> +FIELD(VTYPE, VEDIV, 8, 9)
> +FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
> FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
The ediv definition is wrong -- should be 8, 2.
> @@ -37,4 +38,10 @@ target_ulong fclass_d(uint64_t frs1);
> #define SEW32 2
> #define SEW64 3
>
> +/* table to convert fractional LMUL value */
> +static const float flmul_table[8] = {
> + 1, 2, 4, 8, /* LMUL */
> + -1, /* reserved */
> + 0.125, 0.25, 0.5 /* fractional LMUL */
> +};
> #endif
Don't define data in a header file; only declare it.
> @@ -60,6 +60,9 @@ typedef struct DisasContext {
> /* vector extension */
> bool vill;
> uint8_t lmul;
> + float flmul;
> + uint8_t eew;
> + float emul;
Why are you adding floating-point values to DisasContext?
> +static inline float vext_vflmul(uint32_t desc)
> +{
> + uint32_t lmul = FIELD_EX32(simd_data(desc), VDATA, LMUL);
> + return flmul_table[lmul];
> }
And in the helpers? Are you planning on some sort of path through int -> float
-> int for computation? That seems questionable.
r~
- Re: [RFC v2 10/76] target/riscv: rvv-0.9: add translation-time vector context status, (continued)
- [RFC v2 11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register, frank . chang, 2020/07/22
- [RFC v2 12/76] target/riscv: rvv-0.9: add vcsr register, frank . chang, 2020/07/22
- [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register, frank . chang, 2020/07/22
- [RFC v2 14/76] target/riscv: rvv-0.9: remove MLEN calculations, frank . chang, 2020/07/22
- [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL, frank . chang, 2020/07/22
- Re: [RFC v2 15/76] target/riscv: rvv-0.9: add fractional LMUL,
Richard Henderson <=
- [RFC v2 16/76] target/riscv: rvv-0.9: add VMA and VTA, frank . chang, 2020/07/22
- [RFC v2 17/76] target/riscv: rvv-0.9: update check functions, frank . chang, 2020/07/22
- [RFC v2 18/76] target/riscv: introduce more imm value modes in translator functions, frank . chang, 2020/07/22
- [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper, frank . chang, 2020/07/22