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[RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-exten
From: |
frank . chang |
Subject: |
[RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended |
Date: |
Wed, 22 Jul 2020 17:16:00 +0800 |
From: Frank Chang <frank.chang@sifive.com>
For some vector instructions (e.g. vmv.s.x), the element is loaded with
sign-extended.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 26 ++++++++++++++++++-------
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 3834aca9ab..6b4b7f6574 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -3097,17 +3097,29 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
/* Integer Extract Instruction */
static void load_element(TCGv_i64 dest, TCGv_ptr base,
- int ofs, int sew)
+ int ofs, int sew, bool sign)
{
switch (sew) {
case MO_8:
- tcg_gen_ld8u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld8u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld8s_i64(dest, base, ofs);
+ }
break;
case MO_16:
- tcg_gen_ld16u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld16u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld16s_i64(dest, base, ofs);
+ }
break;
case MO_32:
- tcg_gen_ld32u_i64(dest, base, ofs);
+ if (!sign) {
+ tcg_gen_ld32u_i64(dest, base, ofs);
+ } else {
+ tcg_gen_ld32s_i64(dest, base, ofs);
+ }
break;
case MO_64:
tcg_gen_ld_i64(dest, base, ofs);
@@ -3162,7 +3174,7 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64
dest,
/* Perform the load. */
load_element(dest, base,
- vreg_ofs(s, vreg), s->sew);
+ vreg_ofs(s, vreg), s->sew, false);
tcg_temp_free_ptr(base);
tcg_temp_free_i32(ofs);
@@ -3180,9 +3192,9 @@ static void vec_element_loadx(DisasContext *s, TCGv_i64
dest,
}
static void vec_element_loadi(DisasContext *s, TCGv_i64 dest,
- int vreg, int idx)
+ int vreg, int idx, bool sign)
{
- load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew);
+ load_element(dest, cpu_env, endian_ofs(s, vreg, idx), s->sew, sign);
}
static bool trans_vext_x_v(DisasContext *s, arg_r *a)
--
2.17.1
- [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction, (continued)
- [RFC v2 32/76] target/riscv: rvv-0.9: mask population count instruction, frank . chang, 2020/07/22
- [RFC v2 33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction, frank . chang, 2020/07/22
- [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions, frank . chang, 2020/07/22
- [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction, frank . chang, 2020/07/22
- [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction, frank . chang, 2020/07/22
- [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended,
frank . chang <=
- [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions, frank . chang, 2020/07/22
- [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction, frank . chang, 2020/07/22
- [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/22