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[RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction
From: |
frank . chang |
Subject: |
[RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction |
Date: |
Wed, 22 Jul 2020 17:16:03 +0800 |
From: Frank Chang <frank.chang@sifive.com>
NaN-boxed the scalar floating-point register based on RVV 0.9's rules.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.inc.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c
b/target/riscv/insn_trans/trans_rvv.inc.c
index 780f8660bf..54c08ea1f8 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2722,6 +2722,7 @@ GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
{
if (require_rvv(s) &&
+ has_ext(s, RVF) &&
vext_check_isa_ill(s) &&
require_align(a->rd, s->flmul) &&
(s->sew != 0)) {
@@ -2744,7 +2745,20 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f
*a)
dest = tcg_temp_new_ptr();
desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
- fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+
+ if ((s->sew < MO_64 && has_ext(s, RVD)) ||
+ (s->sew < MO_32)) {
+ /* SEW < FLEN */
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i32 sew = tcg_const_i32(1 << (s->sew + 3));
+ gen_helper_narrower_nanbox_fpr(t1, cpu_fpr[a->rs1],
+ sew, cpu_env);
+ fns[s->sew - 1](dest, t1, cpu_env, desc);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i32(sew);
+ } else {
+ fns[s->sew - 1](dest, cpu_fpr[a->rs1], cpu_env, desc);
+ }
tcg_temp_free_ptr(dest);
tcg_temp_free_i32(desc);
--
2.17.1
- Re: [RFC v2 34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions, (continued)
- [RFC v2 35/76] target/riscv: rvv-0.9: iota instruction, frank . chang, 2020/07/22
- [RFC v2 36/76] target/riscv: rvv-0.9: element index instruction, frank . chang, 2020/07/22
- [RFC v2 37/76] target/riscv: rvv-0.9: allow load element with sign-extended, frank . chang, 2020/07/22
- [RFC v2 38/76] target/riscv: rvv-0.9: register gather instructions, frank . chang, 2020/07/22
- [RFC v2 39/76] target/riscv: rvv-0.9: integer scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 40/76] target/riscv: rvv-0.9: floating-point move instruction,
frank . chang <=
- [RFC v2 41/76] target/riscv: rvv-0.9: floating-point scalar move instructions, frank . chang, 2020/07/22
- [RFC v2 42/76] target/riscv: rvv-0.9: whole register move instructions, frank . chang, 2020/07/22
- [RFC v2 43/76] target/riscv: rvv-0.9: integer extension instructions, frank . chang, 2020/07/22