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Re: [PATCH v1 00/16] RISC-V: Start to remove xlen preprocess
From: |
Bin Meng |
Subject: |
Re: [PATCH v1 00/16] RISC-V: Start to remove xlen preprocess |
Date: |
Mon, 26 Oct 2020 16:55:41 +0800 |
Hi Alistair,
On Fri, Oct 23, 2020 at 11:44 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> The RISC-V QEMU port currently has lot of preprocessor directives that
> check if we are targetting a 32-bit or 64-bit CPU. This means that the
> 64-bit RISC-V target can not run 32-bit CPUs. This is different to most
> other QEMU architectures and doesn't allow us to mix xlens (such as when
> running Hypervisors with different xlen guests).
>
> This series is a step toward removing some of those to allow us to use
> 32-bit CPUs on 64-bit RISC-V targets.
>
> Alistair Francis (16):
> target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
> riscv: spike: Remove target macro conditionals
> riscv: virt: Remove target macro conditionals
> hw/riscv: boot: Remove compile time XLEN checks
> hw/riscv: virt: Remove compile time XLEN checks
> hw/riscv: spike: Remove compile time XLEN checks
> hw/riscv: sifive_u: Remove compile time XLEN checks
> target/riscv: fpu_helper: Match function defs in HELPER macros
> target/riscv: Add a riscv_cpu_is_32bit() helper function
> target/riscv: Specify the XLEN for CPUs
> target/riscv: cpu: Remove compile time XLEN checks
> target/riscv: cpu_helper: Remove compile time XLEN checks
> target/riscv: csr: Remove compile time XLEN checks
> target/riscv: cpu: Set XLEN independently from target
> target/riscv: Convert the get/set_field() to support 64-bit values
> target/riscv: Consolidate *statush registers
>
> include/hw/riscv/boot.h | 8 +-
> include/hw/riscv/spike.h | 6 --
> include/hw/riscv/virt.h | 6 --
> target/riscv/cpu.h | 36 ++++---
> target/riscv/cpu_bits.h | 24 ++---
> hw/riscv/boot.c | 55 ++++++-----
> hw/riscv/sifive_u.c | 59 ++++++------
> hw/riscv/spike.c | 50 +++++-----
> hw/riscv/virt.c | 36 +++----
> target/riscv/cpu.c | 83 ++++++++++------
> target/riscv/cpu_helper.c | 47 +++------
> target/riscv/csr.c | 197 ++++++++++++++++++++------------------
> target/riscv/fpu_helper.c | 16 ++--
> target/riscv/op_helper.c | 11 +--
> 14 files changed, 328 insertions(+), 306 deletions(-)
Test result:
64-bit virt & sifive_u, boots OpenSBI and kernel.
32-bit virt boots OpenSBI and kernel. 32-bit sifive_u does not boot OpenSBI.
Regards,
Bin
- Re: [PATCH v1 12/16] target/riscv: cpu_helper: Remove compile time XLEN checks, (continued)