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Re: [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG mod
From: |
Alistair Francis |
Subject: |
Re: [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module |
Date: |
Tue, 27 Oct 2020 10:42:55 -0700 |
On Tue, Oct 27, 2020 at 7:43 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Previously SYSREG was created as an unimplemented device. Now that
> we have a simple SYSREG module, connect it.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
>
> hw/riscv/Kconfig | 1 +
> hw/riscv/microchip_pfsoc.c | 9 ++++++---
> include/hw/riscv/microchip_pfsoc.h | 2 ++
> 3 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 8f043e38e0..facb0cbacc 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -7,6 +7,7 @@ config MICROCHIP_PFSOC
> select MCHP_PFSOC_DMC
> select MCHP_PFSOC_IOSCB
> select MCHP_PFSOC_MMUART
> + select MCHP_PFSOC_SYSREG
> select MSI_NONBROKEN
> select SIFIVE_CLINT
> select SIFIVE_PDMA
> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
> index 05fb5004a1..69117c6000 100644
> --- a/hw/riscv/microchip_pfsoc.c
> +++ b/hw/riscv/microchip_pfsoc.c
> @@ -135,6 +135,9 @@ static void microchip_pfsoc_soc_instance_init(Object *obj)
> object_initialize_child(obj, "dma-controller", &s->dma,
> TYPE_SIFIVE_PDMA);
>
> + object_initialize_child(obj, "sysreg", &s->sysreg,
> + TYPE_MCHP_PFSOC_SYSREG);
> +
> object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
> TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
> object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
> @@ -262,9 +265,9 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev,
> Error **errp)
> }
>
> /* SYSREG */
> - create_unimplemented_device("microchip.pfsoc.sysreg",
> - memmap[MICROCHIP_PFSOC_SYSREG].base,
> - memmap[MICROCHIP_PFSOC_SYSREG].size);
> + sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
> + memmap[MICROCHIP_PFSOC_SYSREG].base);
>
> /* MPUCFG */
> create_unimplemented_device("microchip.pfsoc.mpucfg",
> diff --git a/include/hw/riscv/microchip_pfsoc.h
> b/include/hw/riscv/microchip_pfsoc.h
> index a244ae6d39..245c82db61 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include/hw/riscv/microchip_pfsoc.h
> @@ -26,6 +26,7 @@
> #include "hw/dma/sifive_pdma.h"
> #include "hw/misc/mchp_pfsoc_dmc.h"
> #include "hw/misc/mchp_pfsoc_ioscb.h"
> +#include "hw/misc/mchp_pfsoc_sysreg.h"
> #include "hw/net/cadence_gem.h"
> #include "hw/sd/cadence_sdhci.h"
>
> @@ -47,6 +48,7 @@ typedef struct MicrochipPFSoCState {
> MchpPfSoCMMUartState *serial2;
> MchpPfSoCMMUartState *serial3;
> MchpPfSoCMMUartState *serial4;
> + MchpPfSoCSysregState sysreg;
> SiFivePDMAState dma;
> CadenceGEMState gem0;
> CadenceGEMState gem1;
> --
> 2.25.1
>
>
- [RESEND PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules, (continued)
- [RESEND PATCH 2/9] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules, Bin Meng, 2020/10/27
- [RESEND PATCH 3/9] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Bin Meng, 2020/10/27
- [RESEND PATCH 4/9] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Bin Meng, 2020/10/27
- [RESEND PATCH 5/9] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Bin Meng, 2020/10/27
- [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Bin Meng, 2020/10/27
- Re: [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module,
Alistair Francis <=
- [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory, Bin Meng, 2020/10/27
- [RESEND PATCH 8/9] hw/riscv: microchip_pfsoc: Correct DDR memory map, Bin Meng, 2020/10/27
- [RESEND PATCH 9/9] hw/riscv: microchip_pfsoc: Hook the I2C1 controller, Bin Meng, 2020/10/27