[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory
|
From: |
Bin Meng |
|
Subject: |
Re: [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory |
|
Date: |
Wed, 28 Oct 2020 10:08:20 +0800 |
Hi Alistair,
On Wed, Oct 28, 2020 at 1:42 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Oct 27, 2020 at 7:53 AM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > Somehow HSS needs to access address 0 [1] for the DDR calibration data
> > which is in the chipset's debug memory. Let's map the debug memory.
> >
> > [1] See the config_copy() calls in various places in ddr_setup() in
> > the HSS source codes.
>
> Really? This is reserved memory that they just read and write to? That's
> crazy.
Yes, that's crazy.
>
> If we really need this can you add a comment saying that the
> documentation is wrong (again) and that this needs to be here.
>
I will try to only map 256 bytes to see how that goes.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > ---
> >
> > hw/riscv/microchip_pfsoc.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
Regards,
Bin
- [RESEND PATCH 3/9] hw/misc: Add Microchip PolarFire SoC IOSCB module support, (continued)
- [RESEND PATCH 3/9] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Bin Meng, 2020/10/27
- [RESEND PATCH 4/9] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Bin Meng, 2020/10/27
- [RESEND PATCH 5/9] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Bin Meng, 2020/10/27
- [RESEND PATCH 6/9] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Bin Meng, 2020/10/27
- [RESEND PATCH 7/9] hw/riscv: microchip_pfsoc: Map debug memory, Bin Meng, 2020/10/27
- [RESEND PATCH 8/9] hw/riscv: microchip_pfsoc: Correct DDR memory map, Bin Meng, 2020/10/27
- [RESEND PATCH 9/9] hw/riscv: microchip_pfsoc: Hook the I2C1 controller, Bin Meng, 2020/10/27