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[PATCH v6 62/72] target/riscv: add "set round to odd" rounding mode help
From: |
frank . chang |
Subject: |
[PATCH v6 62/72] target/riscv: add "set round to odd" rounding mode helper function |
Date: |
Tue, 12 Jan 2021 17:39:36 +0800 |
From: Frank Chang <frank.chang@sifive.com>
helper_set_rounding_mode() is responsible for SIGILL, and "round to odd"
should be an interface private to translation, so add a new independent
helper_set_rod_rounding_mode().
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/fpu_helper.c | 5 +++++
target/riscv/helper.h | 1 +
target/riscv/internals.h | 1 +
target/riscv/translate.c | 5 +++++
4 files changed, 12 insertions(+)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index ad84aeebc1c..ac3e7b4d08f 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -81,6 +81,11 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t
rm)
set_float_rounding_mode(softrm, &env->fp_status);
}
+void helper_set_rod_rounding_mode(CPURISCVState *env)
+{
+ set_float_rounding_mode(float_round_to_odd, &env->fp_status);
+}
+
static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2,
uint64_t rs3, int flags)
{
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index e11cce3e8ea..1d52936c399 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
/* Floating Point - rounding mode */
DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env)
/* Floating Point - fused */
DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 469cc418c4e..6a80c067706 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -43,6 +43,7 @@ enum {
RISCV_FRM_RUP = 3, /* Round Up */
RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
RISCV_FRM_DYN = 7, /* Dynamic rounding mode */
+ RISCV_FRM_ROD = 8, /* Round to Odd */
};
static inline uint64_t nanbox_s(float32 f)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 511b7b868f5..2c9131271e0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -30,6 +30,7 @@
#include "exec/log.h"
#include "instmap.h"
+#include "internals.h"
/* global register indices */
static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
@@ -584,6 +585,10 @@ static void gen_set_rm(DisasContext *ctx, int rm)
return;
}
ctx->frm = rm;
+ if (rm == RISCV_FRM_ROD) {
+ gen_helper_set_rod_rounding_mode(cpu_env);
+ return;
+ }
t0 = tcg_const_i32(rm);
gen_helper_set_rounding_mode(cpu_env, t0);
tcg_temp_free_i32(t0);
--
2.17.1
- [PATCH v6 51/72] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, (continued)
- [PATCH v6 51/72] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/01/12
- [PATCH v6 52/72] target/riscv: rvv-1.0: single-width floating-point reduction, frank . chang, 2021/01/12
- [PATCH v6 53/72] target/riscv: rvv-1.0: widening floating-point reduction instructions, frank . chang, 2021/01/12
- [PATCH v6 54/72] target/riscv: rvv-1.0: single-width scaling shift instructions, frank . chang, 2021/01/12
- [PATCH v6 55/72] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add, frank . chang, 2021/01/12
- [PATCH v6 56/72] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf, frank . chang, 2021/01/12
- [PATCH v6 59/72] target/riscv: introduce floating-point rounding mode enum, frank . chang, 2021/01/12
- [PATCH v6 57/72] target/riscv: rvv-1.0: remove integer extract instruction, frank . chang, 2021/01/12
- [PATCH v6 58/72] target/riscv: rvv-1.0: floating-point min/max instructions, frank . chang, 2021/01/12
- [PATCH v6 60/72] target/riscv: rvv-1.0: floating-point/integer type-convert instructions, frank . chang, 2021/01/12
- [PATCH v6 62/72] target/riscv: add "set round to odd" rounding mode helper function,
frank . chang <=
- [PATCH v6 61/72] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/01/12
- [PATCH v6 63/72] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/01/12
- [PATCH v6 64/72] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/01/12
- [PATCH v6 65/72] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/01/12
- [PATCH v6 67/72] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs, frank . chang, 2021/01/12
- [PATCH v6 66/72] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/01/12
- [PATCH v6 68/72] target/riscv: gdb: modify gdb csr xml file to align with csr register map, frank . chang, 2021/01/12