Re: [PATCH v2 03/37] target/riscv: 16-bit Addition & Subtraction Instructions

[Richard Henderson]

On 6/10/21 12:58 AM, LIU Zhiwei wrote:
> Include 5 groups: Wrap-around (dropping overflow), Signed Halving,
> Unsigned Halving, Signed Saturation, and Unsigned Saturation.
>
> Signed-off-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
> ---
>   include/tcg/tcg-op-gvec.h               |  10 +
>   target/riscv/helper.h                   |  30 ++
>   target/riscv/insn32.decode              |  32 +++
>   target/riscv/insn_trans/trans_rvp.c.inc | 117 ++++++++
>   target/riscv/meson.build                |   1 +
>   target/riscv/packed_helper.c            | 354 ++++++++++++++++++++++++
>   target/riscv/translate.c                |   1 +
>   tcg/tcg-op-gvec.c                       |  28 ++

The tcg part needs to be split out, and I'm happy to give a

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

on that.


r~