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Re: [PATCH v4 15/21] target/riscv: Reorg csr instructions
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From: |
Bin Meng |
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Subject: |
Re: [PATCH v4 15/21] target/riscv: Reorg csr instructions |
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Date: |
Mon, 23 Aug 2021 12:54:19 +0800 |
On Sat, Aug 21, 2021 at 1:43 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Introduce csrr and csrw helpers, for read-only and write-only insns.
>
> Note that we do not properly implement this in riscv_csrrw, in that
> we cannot distinguish true read-only (rs1 == 0) from any other zero
> write_mask another source register -- this should still raise an
> exception for read-only registers.
>
> Only issue gen_io_start for CF_USE_ICOUNT.
> Use ctx->zero for csrrc.
> Use get_gpr and dest_gpr.
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/riscv/helper.h | 6 +-
> target/riscv/op_helper.c | 18 +--
> target/riscv/insn_trans/trans_rvi.c.inc | 172 +++++++++++++++++-------
> 3 files changed, 131 insertions(+), 65 deletions(-)
>
When testing Linux kernel boot, there was a segment fault in the
helper_csrw() path where ret_value pointer is now NULL, and some CSR
write op does not test ret_value.
Regards,
Bin
- [PATCH v4 05/21] target/riscv: Introduce DisasExtend and new helpers, (continued)
- [PATCH v4 05/21] target/riscv: Introduce DisasExtend and new helpers, Richard Henderson, 2021/08/20
- [PATCH v4 06/21] target/riscv: Add DisasExtend to gen_arith*, Richard Henderson, 2021/08/20
- [PATCH v4 08/21] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/08/20
- [PATCH v4 07/21] target/riscv: Remove gen_arith_div*, Richard Henderson, 2021/08/20
- [PATCH v4 09/21] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/20
- [PATCH v4 11/21] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/20
- [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/20
- [PATCH v4 15/21] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/20
- Re: [PATCH v4 15/21] target/riscv: Reorg csr instructions,
Bin Meng <=
- [PATCH v4 12/21] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/20
- [PATCH v4 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/20
- [PATCH v4 14/21] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/20
- [PATCH v4 13/21] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/20
- [PATCH v4 16/21] target/riscv: Use {get,dest}_gpr for RVA, Richard Henderson, 2021/08/20
- [PATCH v4 18/21] target/riscv: Use {get,dest}_gpr for RVF, Richard Henderson, 2021/08/20