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Re: [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB
|
From: |
Alistair Francis |
|
Subject: |
Re: [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB |
|
Date: |
Mon, 23 Aug 2021 16:13:46 +1000 |
On Sat, Aug 21, 2021 at 3:53 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Move these helpers near their use by the trans_*
> functions within insn_trans/trans_rvb.c.inc.
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/translate.c | 233 -----------------------
> target/riscv/insn_trans/trans_rvb.c.inc | 234 ++++++++++++++++++++++++
> 2 files changed, 234 insertions(+), 233 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 7fbacfa6ee..09853530c4 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -380,229 +380,6 @@ static bool gen_arith_imm_tl(DisasContext *ctx, arg_i
> *a, DisasExtend ext,
> return true;
> }
>
> -static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - tcg_gen_deposit_tl(ret, arg1, arg2,
> - TARGET_LONG_BITS / 2,
> - TARGET_LONG_BITS / 2);
> -}
> -
> -static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - TCGv t = tcg_temp_new();
> - tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
> - tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
> - tcg_temp_free(t);
> -}
> -
> -static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - TCGv t = tcg_temp_new();
> - tcg_gen_ext8u_tl(t, arg2);
> - tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
> - tcg_temp_free(t);
> -}
> -
> -static void gen_sbop_mask(TCGv ret, TCGv shamt)
> -{
> - tcg_gen_movi_tl(ret, 1);
> - tcg_gen_shl_tl(ret, ret, shamt);
> -}
> -
> -static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
> -{
> - TCGv t = tcg_temp_new();
> -
> - gen_sbop_mask(t, shamt);
> - tcg_gen_or_tl(ret, arg1, t);
> -
> - tcg_temp_free(t);
> -}
> -
> -static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
> -{
> - TCGv t = tcg_temp_new();
> -
> - gen_sbop_mask(t, shamt);
> - tcg_gen_andc_tl(ret, arg1, t);
> -
> - tcg_temp_free(t);
> -}
> -
> -static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
> -{
> - TCGv t = tcg_temp_new();
> -
> - gen_sbop_mask(t, shamt);
> - tcg_gen_xor_tl(ret, arg1, t);
> -
> - tcg_temp_free(t);
> -}
> -
> -static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
> -{
> - tcg_gen_shr_tl(ret, arg1, shamt);
> - tcg_gen_andi_tl(ret, ret, 1);
> -}
> -
> -static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - tcg_gen_not_tl(ret, arg1);
> - tcg_gen_shl_tl(ret, ret, arg2);
> - tcg_gen_not_tl(ret, ret);
> -}
> -
> -static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - tcg_gen_not_tl(ret, arg1);
> - tcg_gen_shr_tl(ret, ret, arg2);
> - tcg_gen_not_tl(ret, ret);
> -}
> -
> -static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
> -{
> - TCGv source1 = tcg_temp_new();
> - TCGv source2;
> -
> - gen_get_gpr(ctx, source1, a->rs1);
> -
> - if (a->shamt == (TARGET_LONG_BITS - 8)) {
> - /* rev8, byte swaps */
> - tcg_gen_bswap_tl(source1, source1);
> - } else {
> - source2 = tcg_temp_new();
> - tcg_gen_movi_tl(source2, a->shamt);
> - gen_helper_grev(source1, source1, source2);
> - tcg_temp_free(source2);
> - }
> -
> - gen_set_gpr(ctx, a->rd, source1);
> - tcg_temp_free(source1);
> - return true;
> -}
> -
> -#define GEN_SHADD(SHAMT) \
> -static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
> -{ \
> - TCGv t = tcg_temp_new(); \
> - \
> - tcg_gen_shli_tl(t, arg1, SHAMT); \
> - tcg_gen_add_tl(ret, t, arg2); \
> - \
> - tcg_temp_free(t); \
> -}
> -
> -GEN_SHADD(1)
> -GEN_SHADD(2)
> -GEN_SHADD(3)
> -
> -static void gen_ctzw(TCGv ret, TCGv arg1)
> -{
> - tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
> - tcg_gen_ctzi_tl(ret, ret, 64);
> -}
> -
> -static void gen_clzw(TCGv ret, TCGv arg1)
> -{
> - tcg_gen_ext32u_tl(ret, arg1);
> - tcg_gen_clzi_tl(ret, ret, 64);
> - tcg_gen_subi_tl(ret, ret, 32);
> -}
> -
> -static void gen_cpopw(TCGv ret, TCGv arg1)
> -{
> - tcg_gen_ext32u_tl(arg1, arg1);
> - tcg_gen_ctpop_tl(ret, arg1);
> -}
> -
> -static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - TCGv t = tcg_temp_new();
> - tcg_gen_ext16s_tl(t, arg2);
> - tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
> - tcg_temp_free(t);
> -}
> -
> -static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - TCGv t = tcg_temp_new();
> - tcg_gen_shri_tl(t, arg1, 16);
> - tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
> - tcg_gen_ext32s_tl(ret, ret);
> - tcg_temp_free(t);
> -}
> -
> -static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - TCGv_i32 t1 = tcg_temp_new_i32();
> - TCGv_i32 t2 = tcg_temp_new_i32();
> -
> - /* truncate to 32-bits */
> - tcg_gen_trunc_tl_i32(t1, arg1);
> - tcg_gen_trunc_tl_i32(t2, arg2);
> -
> - tcg_gen_rotr_i32(t1, t1, t2);
> -
> - /* sign-extend 64-bits */
> - tcg_gen_ext_i32_tl(ret, t1);
> -
> - tcg_temp_free_i32(t1);
> - tcg_temp_free_i32(t2);
> -}
> -
> -static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - TCGv_i32 t1 = tcg_temp_new_i32();
> - TCGv_i32 t2 = tcg_temp_new_i32();
> -
> - /* truncate to 32-bits */
> - tcg_gen_trunc_tl_i32(t1, arg1);
> - tcg_gen_trunc_tl_i32(t2, arg2);
> -
> - tcg_gen_rotl_i32(t1, t1, t2);
> -
> - /* sign-extend 64-bits */
> - tcg_gen_ext_i32_tl(ret, t1);
> -
> - tcg_temp_free_i32(t1);
> - tcg_temp_free_i32(t2);
> -}
> -
> -static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - tcg_gen_ext32u_tl(arg1, arg1);
> - gen_helper_grev(ret, arg1, arg2);
> -}
> -
> -static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - tcg_gen_ext32u_tl(arg1, arg1);
> - gen_helper_gorcw(ret, arg1, arg2);
> -}
> -
> -#define GEN_SHADD_UW(SHAMT) \
> -static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
> -{ \
> - TCGv t = tcg_temp_new(); \
> - \
> - tcg_gen_ext32u_tl(t, arg1); \
> - \
> - tcg_gen_shli_tl(t, t, SHAMT); \
> - tcg_gen_add_tl(ret, t, arg2); \
> - \
> - tcg_temp_free(t); \
> -}
> -
> -GEN_SHADD_UW(1)
> -GEN_SHADD_UW(2)
> -GEN_SHADD_UW(3)
> -
> -static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
> -{
> - tcg_gen_ext32u_tl(arg1, arg1);
> - tcg_gen_add_tl(ret, arg1, arg2);
> -}
> -
> static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
> void (*func)(TCGv, TCGv, TCGv))
> {
> @@ -701,16 +478,6 @@ static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
> return true;
> }
>
> -static void gen_ctz(TCGv ret, TCGv arg1)
> -{
> - tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
> -}
> -
> -static void gen_clz(TCGv ret, TCGv arg1)
> -{
> - tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
> -}
> -
> static bool gen_unary(DisasContext *ctx, arg_r2 *a,
> void(*func)(TCGv, TCGv))
> {
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index 217a7d1f26..73f088be23 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -17,12 +17,23 @@
> * this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> +
> +static void gen_clz(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
> +}
> +
> static bool trans_clz(DisasContext *ctx, arg_clz *a)
> {
> REQUIRE_EXT(ctx, RVB);
> return gen_unary(ctx, a, gen_clz);
> }
>
> +static void gen_ctz(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
> +}
> +
> static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
> {
> REQUIRE_EXT(ctx, RVB);
> @@ -53,18 +64,41 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
> return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
> }
>
> +static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_deposit_tl(ret, arg1, arg2,
> + TARGET_LONG_BITS / 2,
> + TARGET_LONG_BITS / 2);
> +}
> +
> static bool trans_pack(DisasContext *ctx, arg_pack *a)
> {
> REQUIRE_EXT(ctx, RVB);
> return gen_arith(ctx, a, EXT_NONE, gen_pack);
> }
>
> +static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
> + tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
> + tcg_temp_free(t);
> +}
> +
> static bool trans_packu(DisasContext *ctx, arg_packu *a)
> {
> REQUIRE_EXT(ctx, RVB);
> return gen_arith(ctx, a, EXT_NONE, gen_packu);
> }
>
> +static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_ext8u_tl(t, arg2);
> + tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
> + tcg_temp_free(t);
> +}
> +
> static bool trans_packh(DisasContext *ctx, arg_packh *a)
> {
> REQUIRE_EXT(ctx, RVB);
> @@ -107,6 +141,22 @@ static bool trans_sext_h(DisasContext *ctx, arg_sext_h
> *a)
> return gen_unary(ctx, a, tcg_gen_ext16s_tl);
> }
>
> +static void gen_sbop_mask(TCGv ret, TCGv shamt)
> +{
> + tcg_gen_movi_tl(ret, 1);
> + tcg_gen_shl_tl(ret, ret, shamt);
> +}
> +
> +static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + TCGv t = tcg_temp_new();
> +
> + gen_sbop_mask(t, shamt);
> + tcg_gen_or_tl(ret, arg1, t);
> +
> + tcg_temp_free(t);
> +}
> +
> static bool trans_bset(DisasContext *ctx, arg_bset *a)
> {
> REQUIRE_EXT(ctx, RVB);
> @@ -119,6 +169,16 @@ static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
> return gen_shifti(ctx, a, gen_bset);
> }
>
> +static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + TCGv t = tcg_temp_new();
> +
> + gen_sbop_mask(t, shamt);
> + tcg_gen_andc_tl(ret, arg1, t);
> +
> + tcg_temp_free(t);
> +}
> +
> static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
> {
> REQUIRE_EXT(ctx, RVB);
> @@ -131,6 +191,16 @@ static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
> return gen_shifti(ctx, a, gen_bclr);
> }
>
> +static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + TCGv t = tcg_temp_new();
> +
> + gen_sbop_mask(t, shamt);
> + tcg_gen_xor_tl(ret, arg1, t);
> +
> + tcg_temp_free(t);
> +}
> +
> static bool trans_binv(DisasContext *ctx, arg_binv *a)
> {
> REQUIRE_EXT(ctx, RVB);
> @@ -143,6 +213,12 @@ static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
> return gen_shifti(ctx, a, gen_binv);
> }
>
> +static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
> +{
> + tcg_gen_shr_tl(ret, arg1, shamt);
> + tcg_gen_andi_tl(ret, ret, 1);
> +}
> +
> static bool trans_bext(DisasContext *ctx, arg_bext *a)
> {
> REQUIRE_EXT(ctx, RVB);
> @@ -155,6 +231,13 @@ static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
> return gen_shifti(ctx, a, gen_bext);
> }
>
> +static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_not_tl(ret, arg1);
> + tcg_gen_shl_tl(ret, ret, arg2);
> + tcg_gen_not_tl(ret, ret);
> +}
> +
> static bool trans_slo(DisasContext *ctx, arg_slo *a)
> {
> REQUIRE_EXT(ctx, RVB);
> @@ -167,6 +250,13 @@ static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
> return gen_shifti(ctx, a, gen_slo);
> }
>
> +static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_not_tl(ret, arg1);
> + tcg_gen_shr_tl(ret, ret, arg2);
> + tcg_gen_not_tl(ret, ret);
> +}
> +
> static bool trans_sro(DisasContext *ctx, arg_sro *a)
> {
> REQUIRE_EXT(ctx, RVB);
> @@ -203,6 +293,28 @@ static bool trans_grev(DisasContext *ctx, arg_grev *a)
> return gen_shift(ctx, a, gen_helper_grev);
> }
>
> +static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2;
> +
> + gen_get_gpr(ctx, source1, a->rs1);
> +
> + if (a->shamt == (TARGET_LONG_BITS - 8)) {
> + /* rev8, byte swaps */
> + tcg_gen_bswap_tl(source1, source1);
> + } else {
> + source2 = tcg_temp_new();
> + tcg_gen_movi_tl(source2, a->shamt);
> + gen_helper_grev(source1, source1, source2);
> + tcg_temp_free(source2);
> + }
> +
> + gen_set_gpr(ctx, a->rd, source1);
> + tcg_temp_free(source1);
> + return true;
> +}
> +
> static bool trans_grevi(DisasContext *ctx, arg_grevi *a)
> {
> REQUIRE_EXT(ctx, RVB);
> @@ -226,6 +338,21 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
> return gen_shifti(ctx, a, gen_helper_gorc);
> }
>
> +#define GEN_SHADD(SHAMT) \
> +static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
> +{ \
> + TCGv t = tcg_temp_new(); \
> + \
> + tcg_gen_shli_tl(t, arg1, SHAMT); \
> + tcg_gen_add_tl(ret, t, arg2); \
> + \
> + tcg_temp_free(t); \
> +}
> +
> +GEN_SHADD(1)
> +GEN_SHADD(2)
> +GEN_SHADD(3)
> +
> #define GEN_TRANS_SHADD(SHAMT) \
> static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
> { \
> @@ -237,6 +364,13 @@ GEN_TRANS_SHADD(1)
> GEN_TRANS_SHADD(2)
> GEN_TRANS_SHADD(3)
>
> +static void gen_clzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ext32u_tl(ret, arg1);
> + tcg_gen_clzi_tl(ret, ret, 64);
> + tcg_gen_subi_tl(ret, ret, 32);
> +}
> +
> static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -244,6 +378,12 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
> return gen_unary(ctx, a, gen_clzw);
> }
>
> +static void gen_ctzw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
> + tcg_gen_ctzi_tl(ret, ret, 64);
> +}
> +
> static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -251,6 +391,12 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
> return gen_unary(ctx, a, gen_ctzw);
> }
>
> +static void gen_cpopw(TCGv ret, TCGv arg1)
> +{
> + tcg_gen_ext32u_tl(arg1, arg1);
> + tcg_gen_ctpop_tl(ret, arg1);
> +}
> +
> static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -258,6 +404,14 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
> return gen_unary(ctx, a, gen_cpopw);
> }
>
> +static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_ext16s_tl(t, arg2);
> + tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
> + tcg_temp_free(t);
> +}
> +
> static bool trans_packw(DisasContext *ctx, arg_packw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -265,6 +419,15 @@ static bool trans_packw(DisasContext *ctx, arg_packw *a)
> return gen_arith(ctx, a, EXT_NONE, gen_packw);
> }
>
> +static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv t = tcg_temp_new();
> + tcg_gen_shri_tl(t, arg1, 16);
> + tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
> + tcg_gen_ext32s_tl(ret, ret);
> + tcg_temp_free(t);
> +}
> +
> static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -349,6 +512,24 @@ static bool trans_sroiw(DisasContext *ctx, arg_sroiw *a)
> return gen_shiftiw(ctx, a, gen_sro);
> }
>
> +static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv_i32 t1 = tcg_temp_new_i32();
> + TCGv_i32 t2 = tcg_temp_new_i32();
> +
> + /* truncate to 32-bits */
> + tcg_gen_trunc_tl_i32(t1, arg1);
> + tcg_gen_trunc_tl_i32(t2, arg2);
> +
> + tcg_gen_rotr_i32(t1, t1, t2);
> +
> + /* sign-extend 64-bits */
> + tcg_gen_ext_i32_tl(ret, t1);
> +
> + tcg_temp_free_i32(t1);
> + tcg_temp_free_i32(t2);
> +}
> +
> static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -363,6 +544,24 @@ static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
> return gen_shiftiw(ctx, a, gen_rorw);
> }
>
> +static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + TCGv_i32 t1 = tcg_temp_new_i32();
> + TCGv_i32 t2 = tcg_temp_new_i32();
> +
> + /* truncate to 32-bits */
> + tcg_gen_trunc_tl_i32(t1, arg1);
> + tcg_gen_trunc_tl_i32(t2, arg2);
> +
> + tcg_gen_rotl_i32(t1, t1, t2);
> +
> + /* sign-extend 64-bits */
> + tcg_gen_ext_i32_tl(ret, t1);
> +
> + tcg_temp_free_i32(t1);
> + tcg_temp_free_i32(t2);
> +}
> +
> static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -370,6 +569,12 @@ static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
> return gen_shiftw(ctx, a, gen_rolw);
> }
>
> +static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_ext32u_tl(arg1, arg1);
> + gen_helper_grev(ret, arg1, arg2);
> +}
> +
> static bool trans_grevw(DisasContext *ctx, arg_grevw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -384,6 +589,12 @@ static bool trans_greviw(DisasContext *ctx, arg_greviw
> *a)
> return gen_shiftiw(ctx, a, gen_grevw);
> }
>
> +static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_ext32u_tl(arg1, arg1);
> + gen_helper_gorcw(ret, arg1, arg2);
> +}
> +
> static bool trans_gorcw(DisasContext *ctx, arg_gorcw *a)
> {
> REQUIRE_64BIT(ctx);
> @@ -398,6 +609,23 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw
> *a)
> return gen_shiftiw(ctx, a, gen_gorcw);
> }
>
> +#define GEN_SHADD_UW(SHAMT) \
> +static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
> +{ \
> + TCGv t = tcg_temp_new(); \
> + \
> + tcg_gen_ext32u_tl(t, arg1); \
> + \
> + tcg_gen_shli_tl(t, t, SHAMT); \
> + tcg_gen_add_tl(ret, t, arg2); \
> + \
> + tcg_temp_free(t); \
> +}
> +
> +GEN_SHADD_UW(1)
> +GEN_SHADD_UW(2)
> +GEN_SHADD_UW(3)
> +
> #define GEN_TRANS_SHADD_UW(SHAMT) \
> static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
> arg_sh##SHAMT##add_uw *a) \
> @@ -411,6 +639,12 @@ GEN_TRANS_SHADD_UW(1)
> GEN_TRANS_SHADD_UW(2)
> GEN_TRANS_SHADD_UW(3)
>
> +static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
> +{
> + tcg_gen_ext32u_tl(arg1, arg1);
> + tcg_gen_add_tl(ret, arg1, arg2);
> +}
> +
> static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
> {
> REQUIRE_64BIT(ctx);
> --
> 2.25.1
>
>
- [PATCH v4 01/21] target/riscv: Use tcg_constant_*, (continued)
- [PATCH v4 01/21] target/riscv: Use tcg_constant_*, Richard Henderson, 2021/08/20
- [PATCH v4 04/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr, Richard Henderson, 2021/08/20
- [PATCH v4 05/21] target/riscv: Introduce DisasExtend and new helpers, Richard Henderson, 2021/08/20
- [PATCH v4 06/21] target/riscv: Add DisasExtend to gen_arith*, Richard Henderson, 2021/08/20
- [PATCH v4 08/21] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/08/20
- [PATCH v4 07/21] target/riscv: Remove gen_arith_div*, Richard Henderson, 2021/08/20
- [PATCH v4 09/21] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/20
- [PATCH v4 11/21] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/20
- [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/20
- Re: [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB,
Alistair Francis <=
- [PATCH v4 15/21] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/20
- [PATCH v4 12/21] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/20
- [PATCH v4 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/20
- [PATCH v4 14/21] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/20
- [PATCH v4 13/21] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/20