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Re: [PATCH v5 16/24] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs wr
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v5 16/24] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation |
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Date: |
Wed, 25 Aug 2021 16:08:41 +1000 |
On Tue, Aug 24, 2021 at 6:03 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We distinguish write-only by passing ret_value as NULL.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 23 +++++++++++++++--------
> 1 file changed, 15 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 9a4ed18ac5..d900f96dc1 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -937,9 +937,12 @@ static RISCVException rmw_vsip(CPURISCVState *env, int
> csrno,
> /* Shift the S bits to their VS bit location in mip */
> int ret = rmw_mip(env, 0, ret_value, new_value << 1,
> (write_mask << 1) & vsip_writable_mask & env->hideleg);
> - *ret_value &= VS_MODE_INTERRUPTS;
> - /* Shift the VS bits to their S bit location in vsip */
> - *ret_value >>= 1;
> +
> + if (ret_value) {
> + *ret_value &= VS_MODE_INTERRUPTS;
> + /* Shift the VS bits to their S bit location in vsip */
> + *ret_value >>= 1;
> + }
> return ret;
> }
>
> @@ -956,7 +959,9 @@ static RISCVException rmw_sip(CPURISCVState *env, int
> csrno,
> write_mask & env->mideleg & sip_writable_mask);
> }
>
> - *ret_value &= env->mideleg;
> + if (ret_value) {
> + *ret_value &= env->mideleg;
> + }
> return ret;
> }
>
> @@ -1072,8 +1077,9 @@ static RISCVException rmw_hvip(CPURISCVState *env, int
> csrno,
> int ret = rmw_mip(env, 0, ret_value, new_value,
> write_mask & hvip_writable_mask);
>
> - *ret_value &= hvip_writable_mask;
> -
> + if (ret_value) {
> + *ret_value &= hvip_writable_mask;
> + }
> return ret;
> }
>
> @@ -1084,8 +1090,9 @@ static RISCVException rmw_hip(CPURISCVState *env, int
> csrno,
> int ret = rmw_mip(env, 0, ret_value, new_value,
> write_mask & hip_writable_mask);
>
> - *ret_value &= hip_writable_mask;
> -
> + if (ret_value) {
> + *ret_value &= hip_writable_mask;
> + }
> return ret;
> }
>
> --
> 2.25.1
>
>
- [PATCH v5 06/24] target/riscv: Add DisasExtend to gen_arith*, (continued)
- [PATCH v5 06/24] target/riscv: Add DisasExtend to gen_arith*, Richard Henderson, 2021/08/23
- [PATCH v5 08/24] target/riscv: Use gen_arith for mulh and mulhu, Richard Henderson, 2021/08/23
- [PATCH v5 07/24] target/riscv: Remove gen_arith_div*, Richard Henderson, 2021/08/23
- [PATCH v5 09/24] target/riscv: Move gen_* helpers for RVM, Richard Henderson, 2021/08/23
- [PATCH v5 11/24] target/riscv: Add DisasExtend to gen_unary, Richard Henderson, 2021/08/23
- [PATCH v5 10/24] target/riscv: Move gen_* helpers for RVB, Richard Henderson, 2021/08/23
- [PATCH v5 14/24] target/riscv: Use get_gpr in branches, Richard Henderson, 2021/08/23
- [PATCH v5 12/24] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/23
- [PATCH v5 16/24] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation, Richard Henderson, 2021/08/23
- [PATCH v5 13/24] target/riscv: Use extracts for sraiw and srliw, Richard Henderson, 2021/08/23
- [PATCH v5 15/24] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/23
- [PATCH v5 17/24] target/riscv: Fix hgeie, hgeip, Richard Henderson, 2021/08/23
- [PATCH v5 18/24] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/23
- [PATCH v5 20/24] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/23