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Re: [PATCH v5 17/24] target/riscv: Fix hgeie, hgeip
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v5 17/24] target/riscv: Fix hgeie, hgeip |
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Date: |
Wed, 25 Aug 2021 16:09:33 +1000 |
On Tue, Aug 24, 2021 at 6:08 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> We failed to write into *val for these read functions;
> replace them with read_zero. Only warn about unsupported
> non-zero value when writing a non-zero value.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 26 ++++++++------------------
> 1 file changed, 8 insertions(+), 18 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index d900f96dc1..905860dbb2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1124,17 +1124,12 @@ static RISCVException write_hcounteren(CPURISCVState
> *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static RISCVException read_hgeie(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
> - return RISCV_EXCP_NONE;
> -}
> -
> static RISCVException write_hgeie(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
> + if (val) {
> + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
> + }
> return RISCV_EXCP_NONE;
> }
>
> @@ -1165,17 +1160,12 @@ static RISCVException write_htinst(CPURISCVState
> *env, int csrno,
> return RISCV_EXCP_NONE;
> }
>
> -static RISCVException read_hgeip(CPURISCVState *env, int csrno,
> - target_ulong *val)
> -{
> - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
> - return RISCV_EXCP_NONE;
> -}
> -
> static RISCVException write_hgeip(CPURISCVState *env, int csrno,
> target_ulong val)
> {
> - qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
> + if (val) {
> + qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
> + }
> return RISCV_EXCP_NONE;
> }
>
> @@ -1599,10 +1589,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_HIP] = { "hip", hmode, NULL, NULL, rmw_hip
> },
> [CSR_HIE] = { "hie", hmode, read_hie,
> write_hie },
> [CSR_HCOUNTEREN] = { "hcounteren", hmode, read_hcounteren,
> write_hcounteren },
> - [CSR_HGEIE] = { "hgeie", hmode, read_hgeie,
> write_hgeie },
> + [CSR_HGEIE] = { "hgeie", hmode, read_zero,
> write_hgeie },
> [CSR_HTVAL] = { "htval", hmode, read_htval,
> write_htval },
> [CSR_HTINST] = { "htinst", hmode, read_htinst,
> write_htinst },
> - [CSR_HGEIP] = { "hgeip", hmode, read_hgeip,
> write_hgeip },
> + [CSR_HGEIP] = { "hgeip", hmode, read_zero,
> write_hgeip },
> [CSR_HGATP] = { "hgatp", hmode, read_hgatp,
> write_hgatp },
> [CSR_HTIMEDELTA] = { "htimedelta", hmode, read_htimedelta,
> write_htimedelta },
> [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah,
> write_htimedeltah },
> --
> 2.25.1
>
>
- [PATCH v5 12/24] target/riscv: Use DisasExtend in shift operations, (continued)
- [PATCH v5 12/24] target/riscv: Use DisasExtend in shift operations, Richard Henderson, 2021/08/23
- [PATCH v5 16/24] target/riscv: Fix rmw_sip, rmw_vsip, rmw_hsip vs write-only operation, Richard Henderson, 2021/08/23
- [PATCH v5 13/24] target/riscv: Use extracts for sraiw and srliw, Richard Henderson, 2021/08/23
- [PATCH v5 15/24] target/riscv: Use {get, dest}_gpr for integer load/store, Richard Henderson, 2021/08/23
- [PATCH v5 17/24] target/riscv: Fix hgeie, hgeip, Richard Henderson, 2021/08/23
- [PATCH v5 18/24] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/23
- [PATCH v5 20/24] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/23
- [PATCH v5 19/24] target/riscv: Use {get,dest}_gpr for RVA, Richard Henderson, 2021/08/23
- [PATCH v5 23/24] target/riscv: Tidy trans_rvh.c.inc, Richard Henderson, 2021/08/23
- [PATCH v5 22/24] target/riscv: Use {get,dest}_gpr for RVD, Richard Henderson, 2021/08/23