Re: [PATCH v5 22/24] target/riscv: Use {get,dest}

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Re: [PATCH v5 22/24] target/riscv: Use {get,dest}_gpr for RVD

From:	Alistair Francis
Subject:	Re: [PATCH v5 22/24] target/riscv: Use {get,dest}_gpr for RVD
Date:	Wed, 25 Aug 2021 16:19:36 +1000

On Tue, Aug 24, 2021 at 6:12 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvd.c.inc | 125 ++++++++++++------------
>  1 file changed, 60 insertions(+), 65 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvd.c.inc 
> b/target/riscv/insn_trans/trans_rvd.c.inc
> index 11b9b3f90b..db9ae15755 100644
> --- a/target/riscv/insn_trans/trans_rvd.c.inc
> +++ b/target/riscv/insn_trans/trans_rvd.c.inc
> @@ -20,30 +20,40 @@
>
>  static bool trans_fld(DisasContext *ctx, arg_fld *a)
>  {
> +    TCGv addr;
> +
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> -    tcg_gen_addi_tl(t0, t0, a->imm);
>
> -    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
> +    addr = get_gpr(ctx, a->rs1, EXT_NONE);
> +    if (a->imm) {
> +        TCGv temp = temp_new(ctx);
> +        tcg_gen_addi_tl(temp, addr, a->imm);
> +        addr = temp;
> +    }
> +
> +    tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ);
>
>      mark_fs_dirty(ctx);
> -    tcg_temp_free(t0);
>      return true;
>  }
>
>  static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
>  {
> +    TCGv addr;
> +
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> -    tcg_gen_addi_tl(t0, t0, a->imm);
>
> -    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
> +    addr = get_gpr(ctx, a->rs1, EXT_NONE);
> +    if (a->imm) {
> +        TCGv temp = temp_new(ctx);
> +        tcg_gen_addi_tl(temp, addr, a->imm);
> +        addr = temp;
> +    }
> +
> +    tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ);
>
> -    tcg_temp_free(t0);
>      return true;
>  }
>
> @@ -252,11 +262,10 @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_helper_feq_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    TCGv dest = dest_gpr(ctx, a->rd);
>
> +    gen_helper_feq_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -265,11 +274,10 @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_helper_flt_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    TCGv dest = dest_gpr(ctx, a->rd);
>
> +    gen_helper_flt_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -278,11 +286,10 @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_helper_fle_d(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    TCGv dest = dest_gpr(ctx, a->rd);
>
> +    gen_helper_fle_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -291,10 +298,10 @@ static bool trans_fclass_d(DisasContext *ctx, 
> arg_fclass_d *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +
> +    gen_helper_fclass_d(dest, cpu_fpr[a->rs1]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -303,12 +310,11 @@ static bool trans_fcvt_w_d(DisasContext *ctx, 
> arg_fcvt_w_d *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_w_d(t0, cpu_env, cpu_fpr[a->rs1]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    TCGv dest = dest_gpr(ctx, a->rd);
>
> +    gen_set_rm(ctx, a->rm);
> +    gen_helper_fcvt_w_d(dest, cpu_env, cpu_fpr[a->rs1]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -317,12 +323,11 @@ static bool trans_fcvt_wu_d(DisasContext *ctx, 
> arg_fcvt_wu_d *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_wu_d(t0, cpu_env, cpu_fpr[a->rs1]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    TCGv dest = dest_gpr(ctx, a->rd);
>
> +    gen_set_rm(ctx, a->rm);
> +    gen_helper_fcvt_wu_d(dest, cpu_env, cpu_fpr[a->rs1]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -331,12 +336,10 @@ static bool trans_fcvt_d_w(DisasContext *ctx, 
> arg_fcvt_d_w *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
>
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, t0);
> -    tcg_temp_free(t0);
> +    gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, src);
>
>      mark_fs_dirty(ctx);
>      return true;
> @@ -347,12 +350,10 @@ static bool trans_fcvt_d_wu(DisasContext *ctx, 
> arg_fcvt_d_wu *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
>
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, t0);
> -    tcg_temp_free(t0);
> +    gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, src);
>
>      mark_fs_dirty(ctx);
>      return true;
> @@ -364,11 +365,11 @@ static bool trans_fcvt_l_d(DisasContext *ctx, 
> arg_fcvt_l_d *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_l_d(t0, cpu_env, cpu_fpr[a->rs1]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    gen_helper_fcvt_l_d(dest, cpu_env, cpu_fpr[a->rs1]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -378,11 +379,11 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, 
> arg_fcvt_lu_d *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_lu_d(t0, cpu_env, cpu_fpr[a->rs1]);
> -    gen_set_gpr(ctx, a->rd, t0);
> -    tcg_temp_free(t0);
> +    gen_helper_fcvt_lu_d(dest, cpu_env, cpu_fpr[a->rs1]);
> +    gen_set_gpr(ctx, a->rd, dest);
>      return true;
>  }
>
> @@ -406,12 +407,11 @@ static bool trans_fcvt_d_l(DisasContext *ctx, 
> arg_fcvt_d_l *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_SIGN);
>
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, t0);
> -    tcg_temp_free(t0);
> +    gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, src);
> +
>      mark_fs_dirty(ctx);
>      return true;
>  }
> @@ -422,12 +422,11 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, 
> arg_fcvt_d_lu *a)
>      REQUIRE_FPU;
>      REQUIRE_EXT(ctx, RVD);
>
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> +    TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
>
>      gen_set_rm(ctx, a->rm);
> -    gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, t0);
> -    tcg_temp_free(t0);
> +    gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, src);
> +
>      mark_fs_dirty(ctx);
>      return true;
>  }
> @@ -439,11 +438,7 @@ static bool trans_fmv_d_x(DisasContext *ctx, arg_fmv_d_x 
> *a)
>      REQUIRE_EXT(ctx, RVD);
>
>  #ifdef TARGET_RISCV64
> -    TCGv t0 = tcg_temp_new();
> -    gen_get_gpr(ctx, t0, a->rs1);
> -
> -    tcg_gen_mov_tl(cpu_fpr[a->rd], t0);
> -    tcg_temp_free(t0);
> +    tcg_gen_mov_tl(cpu_fpr[a->rd], get_gpr(ctx, a->rs1, EXT_NONE));
>      mark_fs_dirty(ctx);
>      return true;
>  #else
> --
> 2.25.1
>
>

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Re: [PATCH v5 17/24] target/riscv: Fix hgeie, hgeip, (continued)
- [PATCH v5 18/24] target/riscv: Reorg csr instructions, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 18/24] target/riscv: Reorg csr instructions, Alistair Francis, 2021/08/25
- [PATCH v5 20/24] target/riscv: Use gen_shift_imm_fn for slli_uw, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 20/24] target/riscv: Use gen_shift_imm_fn for slli_uw, Alistair Francis, 2021/08/25
- [PATCH v5 19/24] target/riscv: Use {get,dest}_gpr for RVA, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 19/24] target/riscv: Use {get,dest}_gpr for RVA, Alistair Francis, 2021/08/25
- [PATCH v5 23/24] target/riscv: Tidy trans_rvh.c.inc, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 23/24] target/riscv: Tidy trans_rvh.c.inc, Alistair Francis, 2021/08/30
- [PATCH v5 22/24] target/riscv: Use {get,dest}_gpr for RVD, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 22/24] target/riscv: Use {get,dest}_gpr for RVD, Alistair Francis <=
- [PATCH v5 21/24] target/riscv: Use {get,dest}_gpr for RVF, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 21/24] target/riscv: Use {get,dest}_gpr for RVF, Alistair Francis, 2021/08/25
- [PATCH v5 24/24] target/riscv: Use {get,dest}_gpr for RVV, Richard Henderson, 2021/08/23
  - Re: [PATCH v5 24/24] target/riscv: Use {get,dest}_gpr for RVV, Alistair Francis, 2021/08/30

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