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Re: [PATCH 2/8] target/riscv: 128-bit registers creation and access
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH 2/8] target/riscv: 128-bit registers creation and access |
Date: |
Mon, 30 Aug 2021 23:34:00 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 |
On 8/30/21 7:16 PM, Frédéric Pétrot wrote:
> Addition of the upper 64 bits of the 128-bit registers, along with
> the setter and getter for them and creation of the corresponding
> global tcg values.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> ---
> slirp | 2 +-
> target/riscv/cpu.h | 3 +++
> target/riscv/translate.c | 30 ++++++++++++++++++++++++++++++
> 3 files changed, 34 insertions(+), 1 deletion(-)
>
> diff --git a/slirp b/slirp
> index a88d9ace23..8f43a99191 160000
> --- a/slirp
> +++ b/slirp
> @@ -1 +1 @@
> -Subproject commit a88d9ace234a24ce1c17189642ef9104799425e0
> +Subproject commit 8f43a99191afb47ca3f3c6972f6306209f367ece
Unrelated change...