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[PATCH v2 01/27] memory: add a few defines for octo (128-bit) values
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From: |
Frédéric Pétrot |
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Subject: |
[PATCH v2 01/27] memory: add a few defines for octo (128-bit) values |
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Date: |
Wed, 6 Oct 2021 23:28:07 +0200 |
Introducing unsigned quad, signed quad, and octo accesses types
to handle load and store by 128-bit processors.
This is just a small addition to Richard's patch not yet upstreamed
https://lore.kernel.org/qemu-devel/20210818191920.390759-24-richard.henderson@linaro.org/
Note that the patch must be applied first for the rest to compile
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
include/exec/memop.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 04264ffd6b..9297f58a39 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -85,10 +85,13 @@ typedef enum MemOp {
MO_UB = MO_8,
MO_UW = MO_16,
MO_UL = MO_32,
+ MO_UQ = MO_64,
MO_SB = MO_SIGN | MO_8,
MO_SW = MO_SIGN | MO_16,
MO_SL = MO_SIGN | MO_32,
+ MO_SQ = MO_SIGN | MO_64,
MO_Q = MO_64,
+ MO_O = MO_128,
MO_LEUW = MO_LE | MO_UW,
MO_LEUL = MO_LE | MO_UL,
@@ -105,9 +108,12 @@ typedef enum MemOp {
#ifdef NEED_CPU_H
MO_TEUW = MO_TE | MO_UW,
MO_TEUL = MO_TE | MO_UL,
+ MO_TEUQ = MO_TE | MO_UQ,
MO_TESW = MO_TE | MO_SW,
MO_TESL = MO_TE | MO_SL,
+ MO_TESQ = MO_TE | MO_SQ,
MO_TEQ = MO_TE | MO_Q,
+ MO_TEO = MO_TE | MO_O,
#endif
MO_SSIZE = MO_SIZE | MO_SIGN,
--
2.33.0
- [PATCH v2 00/27] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/10/06
- [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values,
Frédéric Pétrot <=
- [PATCH v2 03/27] target/riscv: adding upper 64 bits for misa, Frédéric Pétrot, 2021/10/06
- [PATCH v2 05/27] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/06
- [PATCH v2 04/27] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 02/27] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/06
- [PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/06
- [PATCH v2 07/27] target/riscv: refactoring calls to gen_arith, Frédéric Pétrot, 2021/10/06
- [PATCH v2 08/27] target/riscv: refactoring calls to gen_shift, Frédéric Pétrot, 2021/10/06
- [PATCH v2 10/27] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/06