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[PATCH v2 10/27] target/riscv: adding accessors to the registers upper p
From: |
Frédéric Pétrot |
Subject: |
[PATCH v2 10/27] target/riscv: adding accessors to the registers upper part |
Date: |
Wed, 6 Oct 2021 23:28:16 +0200 |
Set and get functions to access the 64 top bits of the register, stored
in the gprh field of the cpu state.
It looks as if the access to the gprh field can not be protected to make
sure it is accessed only in the 128-bit version of the processor because
the misa/misah field is writable (as it should since the spec indicates
that the registers size might be dynamically changeable), although it is
for now only set at initialization time.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/translate.c | 45 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0700c82a36..9a74abecdd 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -251,6 +251,25 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num,
DisasExtend ext)
g_assert_not_reached();
}
+/* Make sure high part of registers not accessed when not 128-bit */
+static inline TCGv cpu_gprh_check(DisasContext *ctx, int reg_num)
+{
+ if (is_128bit(ctx)) {
+ return cpu_gprh[reg_num];
+ } else {
+ /* Cannot use qemu_build_not_reached as misa is rw */
+ return 0;
+ }
+}
+
+static TCGv get_gprh(DisasContext *ctx, int reg_num)
+{
+ if (reg_num == 0 || ctx->w) {
+ return ctx->zero;
+ }
+ return cpu_gprh_check(ctx, reg_num);
+}
+
static TCGv dest_gpr(DisasContext *ctx, int reg_num)
{
if (reg_num == 0 || ctx->w) {
@@ -259,6 +278,14 @@ static TCGv dest_gpr(DisasContext *ctx, int reg_num)
return cpu_gpr[reg_num];
}
+static TCGv dest_gprh(DisasContext *ctx, int reg_num)
+{
+ if (reg_num == 0 || ctx->w) {
+ return temp_new(ctx);
+ }
+ return cpu_gprh_check(ctx, reg_num);
+}
+
static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
{
if (reg_num != 0) {
@@ -270,6 +297,17 @@ static void gen_set_gpr(DisasContext *ctx, int reg_num,
TCGv t)
}
}
+static void gen_set_gprh(DisasContext *ctx, int reg_num, TCGv t)
+{
+ if (reg_num != 0) {
+ if (ctx->w) {
+ tcg_gen_sari_tl(cpu_gprh_check(ctx, reg_num), cpu_gpr[reg_num],
63);
+ } else {
+ tcg_gen_mov_tl(cpu_gprh_check(ctx, reg_num), t);
+ }
+ }
+}
+
static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
{
target_ulong next_pc;
@@ -404,6 +442,13 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
DisasExtend ext,
gen_set_gpr(ctx, a->rd, dest);
+ /* Temporary code so that the patch compiles */
+ if (is_128bit(ctx)) {
+ (void)get_gprh(ctx, 6);
+ (void)dest_gprh(ctx, 6);
+ gen_set_gprh(ctx, 6, NULL);
+ }
+
return true;
}
--
2.33.0
- [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values, (continued)
- [PATCH v2 01/27] memory: add a few defines for octo (128-bit) values, Frédéric Pétrot, 2021/10/06
- [PATCH v2 03/27] target/riscv: adding upper 64 bits for misa, Frédéric Pétrot, 2021/10/06
- [PATCH v2 05/27] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/06
- [PATCH v2 04/27] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 02/27] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/06
- [PATCH v2 06/27] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 09/27] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/06
- [PATCH v2 07/27] target/riscv: refactoring calls to gen_arith, Frédéric Pétrot, 2021/10/06
- [PATCH v2 08/27] target/riscv: refactoring calls to gen_shift, Frédéric Pétrot, 2021/10/06
- [PATCH v2 10/27] target/riscv: adding accessors to the registers upper part,
Frédéric Pétrot <=
- [PATCH v2 11/27] target/riscv: handling 128-bit part in logic/arith/shift gen helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 12/27] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 16/27] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/06
- [PATCH v2 15/27] target/riscv: 128-bit support for instructions using gen_shift, Frédéric Pétrot, 2021/10/06
- [PATCH v2 13/27] target/riscv: rename a few gen function helpers, Frédéric Pétrot, 2021/10/06
- [PATCH v2 18/27] target/riscv: 128-bit double word integer shift instructions, Frédéric Pétrot, 2021/10/06
- [PATCH v2 19/27] target/riscv: support for 128-bit base multiplications insns, Frédéric Pétrot, 2021/10/06
- [PATCH v2 14/27] target/riscv: 128-bit support for instructions using gen_arith/gen_logic, Frédéric Pétrot, 2021/10/06
- [PATCH v2 17/27] target/riscv: 128-bit double word integer arithmetic instructions, Frédéric Pétrot, 2021/10/06
- [PATCH v2 21/27] target/riscv: div and rem insns on 128-bit, Frédéric Pétrot, 2021/10/06