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[PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing
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From: |
frank . chang |
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Subject: |
[PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs |
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Date: |
Fri, 15 Oct 2021 15:46:16 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 127393eb956..9f51626a3d8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -297,10 +297,11 @@ static RISCVException write_vxrm(CPURISCVState *env, int
csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
+ target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | sd;
#endif
env->vxrm = val;
@@ -318,10 +319,11 @@ static RISCVException write_vxsat(CPURISCVState *env, int
csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
+ target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | sd;
#endif
env->vxsat = val;
@@ -339,10 +341,11 @@ static RISCVException write_vstart(CPURISCVState *env,
int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
+ target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | sd;
#endif
/*
@@ -362,10 +365,11 @@ static int read_vcsr(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
+ target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
- env->mstatus |= MSTATUS_VS;
+ env->mstatus |= MSTATUS_VS | sd;
#endif
env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
--
2.25.1
- [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert, (continued)
- [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert, frank . chang, 2021/10/15
- [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function, frank . chang, 2021/10/15
- [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert, frank . chang, 2021/10/15
- [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, frank . chang, 2021/10/15
- [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/10/15
- [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/10/15
- [PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs,
frank . chang <=
- [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/10/15
- [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/10/15
- [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/10/15
- [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs, frank . chang, 2021/10/15
- [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/10/15
- [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/10/15
- [PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/10/15