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Re: [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 |
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Date: |
Tue, 26 Oct 2021 16:50:05 +1000 |
On Fri, Oct 15, 2021 at 6:50 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Rename r2_zimm to r2_zimm11 for the upcoming vsetivli instruction.
> vsetivli has 10-bits of zimm but vsetvli has 11-bits of zimm.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 952768f8ded..d7c6bc9af26 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -78,7 +78,7 @@
> @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
> @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
> @r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
> -@r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
> +@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
> @r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
>
> @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
> @@ -671,7 +671,7 @@ vsext_vf2 010010 . ..... 00111 010 ..... 1010111
> @r2_vm
> vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
> vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
>
> -vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
> +vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
>
> # *** RV32 Zba Standard Extension ***
> --
> 2.25.1
>
>
- Re: [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits, (continued)
- [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR, frank . chang, 2021/10/15
- [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid, frank . chang, 2021/10/15
- [PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs, frank . chang, 2021/10/15
- [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32, frank . chang, 2021/10/15
- [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction, frank . chang, 2021/10/15
- [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction, frank . chang, 2021/10/15
- [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs, frank . chang, 2021/10/15
- [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11, frank . chang, 2021/10/15
- Re: [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11,
Alistair Francis <=
- [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction, frank . chang, 2021/10/15
- [PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us(), frank . chang, 2021/10/15
- [PATCH v8 76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns, frank . chang, 2021/10/15
- [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm, frank . chang, 2021/10/15
- [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment, frank . chang, 2021/10/15
- Re: [PATCH v8 00/78] support vector extension v1.0, Frank Chang, 2021/10/15
- Re: [PATCH v8 00/78] support vector extension v1.0, Alistair Francis, 2021/10/18