Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length

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Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length

From:	Richard Henderson
Subject:	Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
Date:	Mon, 25 Oct 2021 07:58:30 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/25/21 2:24 AM, LIU Zhiwei wrote:

I think extending on write is the correct thing.
Thanks. I will pick this way.
Jumps, exception entry and return, gdb write.
If we carefully process jumps and gdb write, I think we can omit exception entry andreturn. Is it right?


No, though you'd probably have to create a special test case to see it.

On exception return, a 64-bit OS can write a 64-bit value into SEPC. But when SEPC iscopied to PC during SRET, UXL should be examined and the assignment should extend for a32-bit user program.

Exception entry would seem to be limited on its face by SXLEN; STVEC will always containthe same number of bits as PC, so no (additional) extension would be required. But we dohave to be careful to interpret the target_ulong value properly for the current SXLEN.

r~

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[PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64, (continued)
- [PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64, Richard Henderson, 2021/10/19
- [PATCH v6 05/15] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/19
- [PATCH v6 12/15] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/19
- [PATCH v6 14/15] target/riscv: Use riscv_csrrw_debug for cpu_dump, Richard Henderson, 2021/10/19
- [PATCH v6 13/15] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/19
- [PATCH v6 15/15] target/riscv: Compute mstatus.sd on demand, Richard Henderson, 2021/10/19
- Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length, Alistair Francis, 2021/10/20
- Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length, LIU Zhiwei, 2021/10/22
  - Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length, Richard Henderson, 2021/10/22
    - Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length, LIU Zhiwei, 2021/10/25
    - Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length, Richard Henderson <=

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