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[ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function
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From: |
Atish Patra |
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Subject: |
[ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function |
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Date: |
Mon, 25 Oct 2021 12:55:52 -0700 |
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/csr.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 23fbbd32162a..1ec776013435 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -89,8 +89,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
- if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
- get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
+ ctr_index = csrno - CSR_CYCLE;
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
+ get_field(env->mcounteren, 1 << ctr_index)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
@@ -116,8 +117,9 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
}
break;
case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
- if (!get_field(env->hcounteren, 1 << (csrno -
CSR_HPMCOUNTER3H)) &&
- get_field(env->mcounteren, 1 << (csrno -
CSR_HPMCOUNTER3H))) {
+ ctr_index = csrno - CSR_CYCLEH;
+ if (!get_field(env->hcounteren, 1 << ctr_index) &&
+ get_field(env->mcounteren, 1 << ctr_index)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
break;
--
2.31.1
- [ PATCH v3 00/10] Improve PMU support, Atish Patra, 2021/10/25
- [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for, Atish Patra, 2021/10/25
- [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu, Atish Patra, 2021/10/25
- [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function,
Atish Patra <=
- [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2021/10/25
- [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR, Atish Patra, 2021/10/25
- [ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation, Atish Patra, 2021/10/25
- [ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents, Atish Patra, 2021/10/25
- [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support, Atish Patra, 2021/10/25
- [ PATCH v3 09/10] target/riscv: Add few cache related PMU events, Atish Patra, 2021/10/25
- [ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree, Atish Patra, 2021/10/25