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[ PATCH v3 09/10] target/riscv: Add few cache related PMU events
From: |
Atish Patra |
Subject: |
[ PATCH v3 09/10] target/riscv: Add few cache related PMU events |
Date: |
Mon, 25 Oct 2021 12:56:00 -0700 |
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
---
target/riscv/cpu_helper.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d41d5cd27c14..66cdfca547cc 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -21,10 +21,13 @@
#include "qemu/log.h"
#include "qemu/main-loop.h"
#include "cpu.h"
+#include "pmu.h"
#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
#include "trace.h"
#include "semihosting/common-semi.h"
+#include "cpu.h"
+#include "cpu_bits.h"
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
@@ -750,6 +753,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr
addr,
}
#endif /* !CONFIG_USER_ONLY */
+
+static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type)
+{
+ enum riscv_pmu_event_idx pmu_event_type;
+
+ switch (access_type) {
+ case MMU_INST_FETCH:
+ pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS;
+ break;
+ case MMU_DATA_LOAD:
+ pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS;
+ break;
+ case MMU_DATA_STORE:
+ pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS;
+ break;
+ default:
+ return;
+ }
+
+ riscv_pmu_incr_ctr(cpu, pmu_event_type);
+}
+
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr)
@@ -847,6 +872,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
}
}
} else {
+ pmu_tlb_fill_incr_ctr(cpu, access_type);
/* Single stage lookup */
ret = get_physical_address(env, &pa, &prot, address, NULL,
access_type, mmu_idx, true, false, false);
--
2.31.1
- [ PATCH v3 00/10] Improve PMU support, Atish Patra, 2021/10/25
- [ PATCH v3 02/10] target/riscv: Implement PMU CSR predicate function for, Atish Patra, 2021/10/25
- [ PATCH v3 03/10] target/riscv: pmu: Rename the counters extension to pmu, Atish Patra, 2021/10/25
- [ PATCH v3 01/10] target/riscv: Fix PMU CSR predicate function, Atish Patra, 2021/10/25
- [ PATCH v3 04/10] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2021/10/25
- [ PATCH v3 05/10] target/riscv: Implement mcountinhibit CSR, Atish Patra, 2021/10/25
- [ PATCH v3 07/10] target/riscv: Support mcycle/minstret write operation, Atish Patra, 2021/10/25
- [ PATCH v3 06/10] target/riscv: Add support for hpmcounters/hpmevents, Atish Patra, 2021/10/25
- [ PATCH v3 08/10] target/riscv: Add sscofpmf extension support, Atish Patra, 2021/10/25
- [ PATCH v3 09/10] target/riscv: Add few cache related PMU events,
Atish Patra <=
- [ PATCH v3 10/10] hw/riscv: virt: Add PMU DT node to the device tree, Atish Patra, 2021/10/25