Re: [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatu

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Re: [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatu

From:	Richard Henderson
Subject:	Re: [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty
Date:	Fri, 29 Oct 2021 12:46:02 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/29/21 1:58 AM, frank.chang@sifive.com wrote:

From: Frank Chang<frank.chang@sifive.com>

Signed-off-by: Frank Chang<frank.chang@sifive.com>
---
  target/riscv/csr.c | 1 +
  1 file changed, 1 insertion(+)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

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[PATCH v9 00/76] support vector extension v1.0, frank . chang, 2021/10/29
- [PATCH v9 01/76] target/riscv: drop vector 0.7.1 and add 1.0 support, frank . chang, 2021/10/29
- [PATCH v9 02/76] target/riscv: Use FIELD_EX32() to extract wd field, frank . chang, 2021/10/29
- [PATCH v9 03/76] target/riscv: rvv-1.0: add mstatus VS field, frank . chang, 2021/10/29
- [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, frank . chang, 2021/10/29
  - Re: [PATCH v9 04/76] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, Richard Henderson <=
- [PATCH v9 06/76] target/riscv: rvv-1.0: introduce writable misa.v field, frank . chang, 2021/10/29
- [PATCH v9 05/76] target/riscv: rvv-1.0: add sstatus VS field, frank . chang, 2021/10/29
- [PATCH v9 07/76] target/riscv: rvv-1.0: add translation-time vector context status, frank . chang, 2021/10/29
- [PATCH v9 08/76] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, frank . chang, 2021/10/29
- [PATCH v9 10/76] target/riscv: rvv-1.0: add vlenb register, frank . chang, 2021/10/29
- [PATCH v9 09/76] target/riscv: rvv-1.0: add vcsr register, frank . chang, 2021/10/29
- [PATCH v9 11/76] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, frank . chang, 2021/10/29
- [PATCH v9 12/76] target/riscv: rvv-1.0: remove MLEN calculations, frank . chang, 2021/10/29
- [PATCH v9 13/76] target/riscv: rvv-1.0: add fractional LMUL, frank . chang, 2021/10/29
- [PATCH v9 14/76] target/riscv: rvv-1.0: add VMA and VTA, frank . chang, 2021/10/29

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