Re: [PATCH v4 11/17] target/riscv: support for 128-bit shift instruction

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Re: [PATCH v4 11/17] target/riscv: support for 128-bit shift instruction

From:	Richard Henderson
Subject:	Re: [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions
Date:	Sat, 30 Oct 2021 21:03:34 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/25/21 5:28 AM, Frédéric Pétrot wrote:

+    if (get_xl(ctx) < MXL_RV128 || max_len < 128) {


Only the second test is required; the first is redundant.

  static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
-                      void (*func)(TCGv, TCGv, TCGv))
+                      void (*func)(TCGv, TCGv, TCGv),
+                      void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv))
  {
-    TCGv dest = dest_gpr(ctx, a->rd);
-    TCGv src1 = get_gpr(ctx, a->rs1, ext);
      TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
      TCGv ext2 = tcg_temp_new();

tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1);

-    func(dest, src1, ext2);

- gen_set_gpr(ctx, a->rd, dest);

+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, ext);
+
+    if (get_xl(ctx) < MXL_RV128 || get_ol(ctx) < MXL_RV128) {

Again, only one test; probably better pulling out max_len, like we did above, since now wequery OL twice.

+}
+
+


Careful with the extra lines.


r~

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Re: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, (continued)
- [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Richard Henderson, 2021/10/30
- [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Richard Henderson, 2021/10/30
- [PATCH v4 07/17] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 07/17] target/riscv: moving some insns close to similar insns, Philippe Mathieu-Daudé, 2021/10/25
- [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions, Richard Henderson, 2021/10/30
- [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions, Richard Henderson <=
- [PATCH v4 13/17] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/10/25
- [PATCH v4 14/17] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/10/25
- [PATCH v4 16/17] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/10/25
- [PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/10/25
- [PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/10/25
- [PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/10/25

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