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Re: [PATCH v4 08/17] target/riscv: accessors to registers upper part and
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From: |
Richard Henderson |
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Subject: |
Re: [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store |
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Date: |
Sat, 30 Oct 2021 20:41:37 -0700 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 |
On 10/25/21 5:28 AM, Frédéric Pétrot wrote:
diff --git a/configs/targets/riscv128-softmmu.mak
b/configs/targets/riscv128-softmmu.mak
index a9343d57d3..41daab1cd3 100644
--- a/configs/targets/riscv128-softmmu.mak
+++ b/configs/targets/riscv128-softmmu.mak
@@ -1,5 +1,6 @@
TARGET_ARCH=riscv128
TARGET_BASE_ARCH=riscv
-TARGET_SUPPORTS_MTTCG=y
+# As long as we have no atomic accesses for aligned 128-bit addresses
+TARGET_SUPPORTS_MTTCG=n
Ah yes, this is why you need the separate executable, at least in the short-term. We
should be able to fix this on the tcg side at some point.
This hunk should be folded back to patch 6.
+static TCGv dest_gprh(DisasContext *ctx, int reg_num)
+{
+ if (reg_num == 0 || get_ol(ctx) < MXL_RV128) {
+ return temp_new(ctx);
+ }
+ return cpu_gprh[reg_num];
+}
You don't need to check get_ol here.
+ if (get_ol(ctx) != MXL_RV128) {
+ g_assert_not_reached();
+ }
This is assert.
+ if (a->imm != 0) {
+ tcg_gen_addi_tl(addrl, src1l, a->imm);
+ } else {
+ tcg_gen_mov_tl(addrl, src1l);
+ }
tcg_gen_addi_tl contains exactly this check; remove it here.
Two instances.
r~
- Re: [PATCH v4 03/17] target/riscv: additional macros to check instruction support, (continued)
- [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/25
- [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/25
- [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/25
- [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/10/25
- Re: [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store,
Richard Henderson <=
- [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/25
- [PATCH v4 07/17] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/25
- [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/25
- [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/25
- [PATCH v4 13/17] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/10/25
- [PATCH v4 14/17] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/10/25