Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations

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Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations

From:	Richard Henderson
Subject:	Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations
Date:	Mon, 25 Oct 2021 13:16:29 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/25/21 8:47 AM, Philippe Mathieu-Daudé wrote:

On 10/25/21 14:28, Frédéric Pétrot wrote:

Addition of not, xor, div and rem on 128-bit integers, used in particular
within div/rem and csr helpers for computations on 128-bit registers in
the 128-bit riscv target.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
  include/qemu/int128.h |  26 +++++
  util/int128.c         | 218 ++++++++++++++++++++++++++++++++++++++++++
  util/meson.build      |   1 +
  3 files changed, 245 insertions(+)
  create mode 100644 util/int128.c


If you ever have to respin, please split the logical operations in
one patch and the div/rem in another.

I have pulled out these logicals into a separate patch and applied to tcg-next. I'llhandle division relative to the PPC64 DFP patch set.

r~

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[PATCH v4 00/17] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/10/25
- [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers, Philippe Mathieu-Daudé, 2021/10/25
  - Re: [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers, Richard Henderson, 2021/10/25
- [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO, Richard Henderson, 2021/10/25
- [PATCH v4 03/17] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 03/17] target/riscv: additional macros to check instruction support, Richard Henderson, 2021/10/30
- [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Philippe Mathieu-Daudé, 2021/10/25
    - Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Richard Henderson <=
- [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Philippe Mathieu-Daudé, 2021/10/25
  - Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Richard Henderson, 2021/10/25
- [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Richard Henderson, 2021/10/30
- [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Richard Henderson, 2021/10/30
- [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Richard Henderson, 2021/10/30
- [PATCH v4 07/17] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/25

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