Re: [PATCH v2 14/14] target/riscv: Enable uxl field write

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Re: [PATCH v2 14/14] target/riscv: Enable uxl field write

From:	Richard Henderson
Subject:	Re: [PATCH v2 14/14] target/riscv: Enable uxl field write
Date:	Wed, 10 Nov 2021 16:02:35 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 11/10/21 3:38 PM, LIU Zhiwei wrote:

Why do you not allow writes to SXL?


That means we still don't support the change of SXLEN.
I didn't check the S-mode CSRs behavior when XLEN changes in this patch set.

For example, the behavior of satp when trap into M-mode from S-mode if SXLEN=32 
and MXLEN=64.


Ah, good answer.


r~

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Re: [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN, (continued)
- [PATCH v2 12/14] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, Richard Henderson, 2021/11/10
    - Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/10
    - Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, Richard Henderson, 2021/11/10
- [PATCH v2 13/14] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 13/14] target/riscv: Don't save pc when exception return, Richard Henderson, 2021/11/10
- [PATCH v2 14/14] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 14/14] target/riscv: Enable uxl field write, Richard Henderson, 2021/11/10
    - Re: [PATCH v2 14/14] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/10
    - Re: [PATCH v2 14/14] target/riscv: Enable uxl field write, Richard Henderson <=

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