Re: [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN

qemu-riscv

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN

From:	Richard Henderson
Subject:	Re: [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN
Date:	Wed, 10 Nov 2021 12:29:50 +0100
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 11/10/21 8:04 AM, LIU Zhiwei wrote:

diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index b15ad394bb..07e882160d 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -27,6 +27,7 @@ FIELD(VDATA, VM, 8, 1)
  FIELD(VDATA, LMUL, 9, 2)
  FIELD(VDATA, NF, 11, 4)
  FIELD(VDATA, WD, 11, 1)
+FIELD(VDATA, TRUNC, 15, 1)


No need for this.

@@ -4756,7 +4762,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, 
void *vs2,         \
              continue;                                                     \
          }                                                                 \
          if (i == 0) {                                                     \
-            *((ETYPE *)vd + H(i)) = s1;                                   \
+            *((ETYPE *)vd + H(i)) = trunc ? (s1 & UINT32_MAX) : s1;       \
          } else {                                                          \
              *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1));           \
          }                                                                 \

...

@@ -4785,7 +4792,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, 
void *vs2,         \
              continue;                                                     \
          }                                                                 \
          if (i == vl - 1) {                                                \
-            *((ETYPE *)vd + H(i)) = s1;                                   \
+            *((ETYPE *)vd + H(i)) = trunc ? (s1 & UINT32_MAX) : s1;       \


In both of these cases you can simply zero-extend s1 in the translator before 
passing it in.


r~

[Prev in Thread]

Current Thread

[Next in Thread]

[PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN, (continued)
- [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 07/14] target/riscv: Ajdust vector atomic check with XLEN, Richard Henderson, 2021/11/10
- [PATCH v2 08/14] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2021/11/10
- [PATCH v2 09/14] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 09/14] target/riscv: Relax debug check for pm write, Richard Henderson, 2021/11/10
- [PATCH v2 10/14] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask, Richard Henderson, 2021/11/10
    - Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2021/11/10
    - Re: [PATCH v2 10/14] target/riscv: Adjust vector address with mask, Richard Henderson, 2021/11/10
- [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN, Richard Henderson <=
- [PATCH v2 12/14] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, Richard Henderson, 2021/11/10
    - Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/10
    - Re: [PATCH v2 12/14] target/riscv: Split out the vill from vtype, Richard Henderson, 2021/11/10
- [PATCH v2 13/14] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 13/14] target/riscv: Don't save pc when exception return, Richard Henderson, 2021/11/10
- [PATCH v2 14/14] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/10
  - Re: [PATCH v2 14/14] target/riscv: Enable uxl field write, Richard Henderson, 2021/11/10
    - Re: [PATCH v2 14/14] target/riscv: Enable uxl field write, LIU Zhiwei, 2021/11/10
    - Re: [PATCH v2 14/14] target/riscv: Enable uxl field write, Richard Henderson, 2021/11/10

Prev by Date: Re: [PATCH v2 14/14] target/riscv: Enable uxl field write
Next by Date: Re: [PATCH v2 09/14] target/riscv: Relax debug check for pm write
Previous by thread: [PATCH v2 11/14] target/riscv: Adjust scalar reg in vector with XLEN
Next by thread: [PATCH v2 12/14] target/riscv: Split out the vill from vtype
Index(es):
- Date
- Thread