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Re: [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN


From: LIU Zhiwei
Subject: Re: [PATCH v3 19/20] target/riscv: Adjust scalar reg in vector with XLEN
Date: Thu, 11 Nov 2021 22:43:42 +0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 2021/11/11 下午7:46, Richard Henderson wrote:

On 11/11/21 6:57 AM, LIU Zhiwei wrote:
@@ -2670,6 +2672,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
          /* This instruction ignores LMUL and vector register groups */
          int maxsz = s->vlen >> 3;
          TCGv_i64 t1;
+        TCGv src1 = get_gpr(s, a->rs1, EXT_ZERO);

A reminder that this is zero-extend for v0.7.1 and sign-extend for v1.0.0.

@@ -2679,7 +2682,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
          }
            t1 = tcg_temp_new_i64();
-        tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+        tcg_gen_extu_tl_i64(t1, src1);

Likewise.

          vec_element_storei(s, a->rd, 0, t1);
          tcg_temp_free_i64(t1);
      done:
@@ -2748,12 +2751,28 @@ static bool slideup_check(DisasContext *s, arg_rmrr *a)
              (a->rd != a->rs2));
  }
  +/* OPIVXU without GVEC IR */
+#define GEN_OPIVXU_TRANS(NAME, CHECK)                                    \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
+{ \
+    if (CHECK(s, a)) {                                                   \ +        static gen_helper_opivx * const fns[4] = {                       \ +            gen_helper_##NAME##_b, gen_helper_##NAME##_h,                \ +            gen_helper_##NAME##_w, gen_helper_##NAME##_d,                \
+ }; \
+ \
+        return opivx_trans(a->rd, a->rs1, a->rs2, a->vm,                 \ +                           fns[s->sew], s, EXT_ZERO);                    \
+ } \
+    return false;                                                        \
+}
+
  GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
-GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
+GEN_OPIVXU_TRANS(vslide1up_vx, slideup_check)
  GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
    GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
-GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
+GEN_OPIVXU_TRANS(vslide1down_vx, opivx_check)
  GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)

Likewise.

So if this patch set goes in after rvv 1.0, this whole patch may be dropped.

Got it.

Thanks,
Zhiwei


r~



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