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[PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN |
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Date: |
Thu, 25 Nov 2021 15:39:34 +0800 |
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b6cddf8648..9c3838bddf 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -71,7 +71,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong
*pc,
{
uint32_t flags = 0;
- *pc = env->pc;
+ *pc = env->xl == MXL_RV32 ? env->pc & UINT32_MAX : env->pc;
*cs_base = 0;
if (riscv_has_ext(env, RVV)) {
@@ -127,7 +127,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong
*pc,
}
#endif
- flags = FIELD_DP32(flags, TB_FLAGS, XL, cpu_get_xl(env));
+ flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl);
*pflags = flags;
}
--
2.25.1
- [PATCH v5 00/22] Support UXL filed in xstatus, LIU Zhiwei, 2021/11/25
- [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl, LIU Zhiwei, 2021/11/25
- [PATCH v5 02/22] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2021/11/25
- [PATCH v5 03/22] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 04/22] target/riscv: Create xl field in env, LIU Zhiwei, 2021/11/25
- [PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN,
LIU Zhiwei <=
- [PATCH v5 06/22] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2021/11/25
- [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/25
- [PATCH v5 08/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2021/11/25
- [PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 10/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2021/11/25
- [PATCH v5 11/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2021/11/25
- [PATCH v5 12/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2021/11/25
- [PATCH v5 14/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/25