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[PATCH v5 08/22] target/riscv: Relax debug check for pm write
From: |
LIU Zhiwei |
Subject: |
[PATCH v5 08/22] target/riscv: Relax debug check for pm write |
Date: |
Thu, 25 Nov 2021 15:39:37 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d4ee897be2..bfafd3bd96 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1465,6 +1465,9 @@ static bool check_pm_current_disabled(CPURISCVState *env,
int csrno)
int csr_priv = get_field(csrno, 0x300);
int pm_current;
+ if (env->debugger) {
+ return false;
+ }
/*
* If priv lvls differ that means we're accessing csr from higher priv lvl,
* so allow the access
--
2.25.1
- [PATCH v5 00/22] Support UXL filed in xstatus, LIU Zhiwei, 2021/11/25
- [PATCH v5 01/22] target/riscv: Adjust pmpcfg access with mxl, LIU Zhiwei, 2021/11/25
- [PATCH v5 02/22] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2021/11/25
- [PATCH v5 03/22] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 04/22] target/riscv: Create xl field in env, LIU Zhiwei, 2021/11/25
- [PATCH v5 05/22] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 06/22] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2021/11/25
- [PATCH v5 07/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2021/11/25
- [PATCH v5 08/22] target/riscv: Relax debug check for pm write,
LIU Zhiwei <=
- [PATCH v5 09/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 10/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2021/11/25
- [PATCH v5 11/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2021/11/25
- [PATCH v5 12/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 13/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2021/11/25
- [PATCH v5 14/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2021/11/25
- [PATCH v5 15/22] target/riscv: Fix RESERVED field length in VTYPE, LIU Zhiwei, 2021/11/25
- [PATCH v5 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2021/11/25
- [PATCH v5 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2021/11/25