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Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len
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From: |
Bin Meng |
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Subject: |
Re: [PATCH 1/2] riscv: opentitan: fixup plic stride len |
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Date: |
Mon, 10 Jan 2022 15:34:01 +0800 |
On Mon, Jan 10, 2022 at 2:13 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following change was made to rectify incorrectly set stride length
> on the PLIC. Where it should be 32bit and not 24bit (0x18). This was
PLIC [1]
> discovered whilst attempting to fix a bug where a timer_interrupt was
> not serviced on TockOS-OpenTitan.
>
[1] https://docs.opentitan.org/hw/top_earlgrey/ip_autogen/rv_plic/doc/
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
> hw/riscv/opentitan.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>