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[PATCH v5 05/13] target/riscv: Implement kvm_arch_put_registers
From: |
Yifei Jiang |
Subject: |
[PATCH v5 05/13] target/riscv: Implement kvm_arch_put_registers |
Date: |
Wed, 12 Jan 2022 16:13:21 +0800 |
Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/kvm.c | 104 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 103 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 039af22125..dbaff53bf2 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -74,6 +74,14 @@ static uint64_t kvm_riscv_reg_id(CPURISCVState *env,
uint64_t type,
} \
} while (0)
+#define KVM_RISCV_SET_CSR(cs, env, csr, reg) \
+ do { \
+ int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), ®); \
+ if (ret) { \
+ return ret; \
+ } \
+ } while (0)
+
static int kvm_riscv_get_regs_core(CPUState *cs)
{
int ret = 0;
@@ -99,6 +107,31 @@ static int kvm_riscv_get_regs_core(CPUState *cs)
return ret;
}
+static int kvm_riscv_put_regs_core(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ target_ulong reg;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ reg = env->pc;
+ ret = kvm_set_one_reg(cs, RISCV_CORE_REG(env, regs.pc), ®);
+ if (ret) {
+ return ret;
+ }
+
+ for (i = 1; i < 32; i++) {
+ uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
+ reg = env->gpr[i];
+ ret = kvm_set_one_reg(cs, id, ®);
+ if (ret) {
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static int kvm_riscv_get_regs_csr(CPUState *cs)
{
int ret = 0;
@@ -116,6 +149,24 @@ static int kvm_riscv_get_regs_csr(CPUState *cs)
return ret;
}
+static int kvm_riscv_put_regs_csr(CPUState *cs)
+{
+ int ret = 0;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
+ KVM_RISCV_SET_CSR(cs, env, sie, env->mie);
+ KVM_RISCV_SET_CSR(cs, env, stvec, env->stvec);
+ KVM_RISCV_SET_CSR(cs, env, sscratch, env->sscratch);
+ KVM_RISCV_SET_CSR(cs, env, sepc, env->sepc);
+ KVM_RISCV_SET_CSR(cs, env, scause, env->scause);
+ KVM_RISCV_SET_CSR(cs, env, stval, env->stval);
+ KVM_RISCV_SET_CSR(cs, env, sip, env->mip);
+ KVM_RISCV_SET_CSR(cs, env, satp, env->satp);
+
+ return ret;
+}
+
static int kvm_riscv_get_regs_fp(CPUState *cs)
{
int ret = 0;
@@ -149,6 +200,40 @@ static int kvm_riscv_get_regs_fp(CPUState *cs)
return ret;
}
+static int kvm_riscv_put_regs_fp(CPUState *cs)
+{
+ int ret = 0;
+ int i;
+ CPURISCVState *env = &RISCV_CPU(cs)->env;
+
+ if (riscv_has_ext(env, RVD)) {
+ uint64_t reg;
+ for (i = 0; i < 32; i++) {
+ reg = env->fpr[i];
+ ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®);
+ if (ret) {
+ return ret;
+ }
+ }
+ return ret;
+ }
+
+ if (riscv_has_ext(env, RVF)) {
+ uint32_t reg;
+ for (i = 0; i < 32; i++) {
+ reg = env->fpr[i];
+ ret = kvm_set_one_reg(cs, RISCV_FP_F_REG(env, i), ®);
+ if (ret) {
+ return ret;
+ }
+ }
+ return ret;
+ }
+
+ return ret;
+}
+
+
const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
KVM_CAP_LAST_INFO
};
@@ -177,7 +262,24 @@ int kvm_arch_get_registers(CPUState *cs)
int kvm_arch_put_registers(CPUState *cs, int level)
{
- return 0;
+ int ret = 0;
+
+ ret = kvm_riscv_put_regs_core(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_put_regs_csr(cs);
+ if (ret) {
+ return ret;
+ }
+
+ ret = kvm_riscv_put_regs_fp(cs);
+ if (ret) {
+ return ret;
+ }
+
+ return ret;
}
int kvm_arch_release_virq_post(int virq)
--
2.19.1
- [PATCH v5 00/13] Add riscv kvm accel support, Yifei Jiang, 2022/01/12
- [PATCH v5 01/13] update-linux-headers: Add asm-riscv/kvm.h, Yifei Jiang, 2022/01/12
- [PATCH v5 02/13] target/riscv: Add target/riscv/kvm.c to place the public kvm interface, Yifei Jiang, 2022/01/12
- [PATCH v5 03/13] target/riscv: Implement function kvm_arch_init_vcpu, Yifei Jiang, 2022/01/12
- [PATCH v5 04/13] target/riscv: Implement kvm_arch_get_registers, Yifei Jiang, 2022/01/12
- [PATCH v5 05/13] target/riscv: Implement kvm_arch_put_registers,
Yifei Jiang <=
- [PATCH v5 06/13] target/riscv: Support start kernel directly by KVM, Yifei Jiang, 2022/01/12
- [PATCH v5 07/13] target/riscv: Support setting external interrupt by KVM, Yifei Jiang, 2022/01/12
- [PATCH v5 08/13] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Yifei Jiang, 2022/01/12
- [PATCH v5 09/13] target/riscv: Add host cpu type, Yifei Jiang, 2022/01/12
- [PATCH v5 10/13] target/riscv: Add kvm_riscv_get/put_regs_timer, Yifei Jiang, 2022/01/12
- [PATCH v5 11/13] target/riscv: Implement virtual time adjusting with vm state changing, Yifei Jiang, 2022/01/12
- [PATCH v5 12/13] target/riscv: Support virtual time context synchronization, Yifei Jiang, 2022/01/12
- [PATCH v5 13/13] target/riscv: enable riscv kvm accel, Yifei Jiang, 2022/01/12