[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v6 09/22] target/riscv: Relax debug check for pm write
From: |
LIU Zhiwei |
Subject: |
[PATCH v6 09/22] target/riscv: Relax debug check for pm write |
Date: |
Thu, 13 Jan 2022 19:39:51 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b282a642f5..3f3afbed21 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1552,6 +1552,9 @@ static bool check_pm_current_disabled(CPURISCVState *env,
int csrno)
int csr_priv = get_field(csrno, 0x300);
int pm_current;
+ if (env->debugger) {
+ return false;
+ }
/*
* If priv lvls differ that means we're accessing csr from higher priv lvl,
* so allow the access
--
2.25.1
- [PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr, (continued)
- [PATCH v6 06/22] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 07/22] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2022/01/13
- [PATCH v6 08/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2022/01/13
- [PATCH v6 09/22] target/riscv: Relax debug check for pm write,
LIU Zhiwei <=
- [PATCH v6 10/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 11/22] target/riscv: Create current pm fields in env, LIU Zhiwei, 2022/01/13
- [PATCH v6 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2022/01/13
- [PATCH v6 13/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 14/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/13
- [PATCH v6 15/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/13
- [PATCH v6 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2022/01/13
- [PATCH v6 18/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2022/01/13
- [PATCH v6 19/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2022/01/13