[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr
|
From: |
Alistair Francis |
|
Subject: |
Re: [PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr |
|
Date: |
Wed, 19 Jan 2022 13:21:19 +1000 |
On Thu, Jan 13, 2022 at 9:45 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 4 +---
> target/riscv/translate.c | 4 +---
> 2 files changed, 2 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index 3a0ae28fef..b9ba57f266 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -68,9 +68,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
> tcg_temp_free(t0);
> }
>
> - if (a->rd != 0) {
> - tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
> - }
> + gen_set_gpri(ctx, a->rd, ctx->pc_succ_insn);
> tcg_gen_lookup_and_goto_ptr();
>
> if (misaligned) {
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 615048ec87..b47b308920 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -367,10 +367,8 @@ static void gen_jal(DisasContext *ctx, int rd,
> target_ulong imm)
> return;
> }
> }
> - if (rd != 0) {
> - tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn);
> - }
>
> + gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
> gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for
> safety */
> ctx->base.is_jmp = DISAS_NORETURN;
> }
> --
> 2.25.1
>
>
- [PATCH v6 00/22] Support UXL filed in xstatus, LIU Zhiwei, 2022/01/13
- [PATCH v6 01/22] target/riscv: Adjust pmpcfg access with mxl, LIU Zhiwei, 2022/01/13
- [PATCH v6 02/22] target/riscv: Don't save pc when exception return, LIU Zhiwei, 2022/01/13
- [PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr, LIU Zhiwei, 2022/01/13
- Re: [PATCH v6 03/22] target/riscv: Sign extend link reg for jal and jalr,
Alistair Francis <=
- [PATCH v6 04/22] target/riscv: Sign extend pc for different XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 05/22] target/riscv: Create xl field in env, LIU Zhiwei, 2022/01/13
- [PATCH v6 06/22] target/riscv: Ignore the pc bits above XLEN, LIU Zhiwei, 2022/01/13
- [PATCH v6 07/22] target/riscv: Extend pc for runtime pc write, LIU Zhiwei, 2022/01/13
- [PATCH v6 08/22] target/riscv: Use gdb xml according to max mxlen, LIU Zhiwei, 2022/01/13
- [PATCH v6 09/22] target/riscv: Relax debug check for pm write, LIU Zhiwei, 2022/01/13
- [PATCH v6 10/22] target/riscv: Adjust csr write mask with XLEN, LIU Zhiwei, 2022/01/13