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[PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be tur
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From: |
frank . chang |
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Subject: |
[PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on |
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Date: |
Tue, 18 Jan 2022 09:45:13 +0800 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2ba22503da..4bca1cd289 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -664,6 +664,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
+ DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
--
2.31.1
- [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions, frank . chang, 2022/01/17
- [PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns, frank . chang, 2022/01/17
- [PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, frank . chang, 2022/01/17
- [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns, frank . chang, 2022/01/17
- [PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, frank . chang, 2022/01/17
- [PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, frank . chang, 2022/01/17
- [PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, frank . chang, 2022/01/17
- [PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, frank . chang, 2022/01/17
- [PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, frank . chang, 2022/01/17
- [PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on,
frank . chang <=
- [PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns, frank . chang, 2022/01/17
- [PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns, frank . chang, 2022/01/17
- [PATCH v2 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns, frank . chang, 2022/01/17
- [PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns, frank . chang, 2022/01/17
- [PATCH v2 13/17] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns, frank . chang, 2022/01/17
- [PATCH v2 15/17] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns, frank . chang, 2022/01/17
- [PATCH v2 16/17] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns, frank . chang, 2022/01/17
- [PATCH v2 17/17] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on, frank . chang, 2022/01/17
- Re: [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions, Alistair Francis, 2022/01/18