[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load
From: |
Alistair Francis |
Subject: |
Re: [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns |
Date: |
Tue, 18 Jan 2022 14:42:43 +1000 |
On Tue, Jan 18, 2022 at 11:59 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> All Zve* extensions support all vector load and store instructions,
> except Zve64* extensions do not support EEW=64 for index values when
> XLEN=32.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 19 +++++++++++++++----
> 1 file changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 5b47729a21..0bf41aaa1e 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -263,10 +263,21 @@ static bool vext_check_st_index(DisasContext *s, int
> vd, int vs2, int nf,
> uint8_t eew)
> {
> int8_t emul = eew - s->sew + s->lmul;
> - return (emul >= -3 && emul <= 3) &&
> - require_align(vs2, emul) &&
> - require_align(vd, s->lmul) &&
> - require_nf(vd, nf, s->lmul);
> + bool ret = (emul >= -3 && emul <= 3) &&
> + require_align(vs2, emul) &&
> + require_align(vd, s->lmul) &&
> + require_nf(vd, nf, s->lmul);
> +
> + /*
> + * All Zve* extensions support all vector load and store instructions,
> + * except Zve64* extensions do not support EEW=64 for index values
> + * when XLEN=32. (Section 18.2)
> + */
> + if (get_xl(s) == MXL_RV32) {
> + ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true);
> + }
> +
> + return ret;
> }
>
> /*
> --
> 2.31.1
>
>
- [PATCH v2 00/17] Add RISC-V RVV Zve32f and Zve64f extensions, frank . chang, 2022/01/17
- [PATCH v2 02/17] target/riscv: rvv-1.0: Add Zve64f support for configuration insns, frank . chang, 2022/01/17
- [PATCH v2 01/17] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V, frank . chang, 2022/01/17
- [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns, frank . chang, 2022/01/17
- Re: [PATCH v2 03/17] target/riscv: rvv-1.0: Add Zve64f support for load and store insns,
Alistair Francis <=
- [PATCH v2 05/17] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns, frank . chang, 2022/01/17
- [PATCH v2 04/17] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns, frank . chang, 2022/01/17
- [PATCH v2 06/17] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns, frank . chang, 2022/01/17
- [PATCH v2 07/17] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns, frank . chang, 2022/01/17
- [PATCH v2 11/17] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V, frank . chang, 2022/01/17
- [PATCH v2 10/17] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on, frank . chang, 2022/01/17
- [PATCH v2 09/17] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns, frank . chang, 2022/01/17
- [PATCH v2 08/17] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns, frank . chang, 2022/01/17
- [PATCH v2 12/17] target/riscv: rvv-1.0: Add Zve32f support for configuration insns, frank . chang, 2022/01/17
- [PATCH v2 14/17] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns, frank . chang, 2022/01/17