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Re: [PATCH v7 21/22] target/riscv: Enable uxl field write
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v7 21/22] target/riscv: Enable uxl field write |
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Date: |
Thu, 20 Jan 2022 10:35:36 +1000 |
On Wed, Jan 19, 2022 at 3:34 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/csr.c | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index b11d92b51b..90f78eca65 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -572,6 +572,7 @@ static RISCVException write_mstatus(CPURISCVState *env,
> int csrno,
> {
> uint64_t mstatus = env->mstatus;
> uint64_t mask = 0;
> + RISCVMXL xl = riscv_cpu_mxl(env);
>
> /* flush tlb on mstatus fields that affect VM */
> if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
> @@ -583,21 +584,22 @@ static RISCVException write_mstatus(CPURISCVState *env,
> int csrno,
> MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
> MSTATUS_TW | MSTATUS_VS;
>
> - if (riscv_cpu_mxl(env) != MXL_RV32) {
> + if (xl != MXL_RV32) {
> /*
> * RV32: MPV and GVA are not in mstatus. The current plan is to
> * add them to mstatush. For now, we just don't support it.
> */
> mask |= MSTATUS_MPV | MSTATUS_GVA;
> + if ((val & MSTATUS64_UXL) != 0) {
> + mask |= MSTATUS64_UXL;
> + }
> }
>
> mstatus = (mstatus & ~mask) | (val & mask);
>
> - RISCVMXL xl = riscv_cpu_mxl(env);
> if (xl > MXL_RV32) {
> - /* SXL and UXL fields are for now read only */
> + /* SXL field is for now read only */
> mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
> - mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
This change causes:
ERROR:../target/riscv/translate.c:295:get_gpr: code should not be reached
to assert when running an Xvisor (Hypervisor extension) guest on the
64-bit virt machine.
Alistair
- [PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base], (continued)
- [PATCH v7 12/22] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2022/01/19
- [PATCH v7 13/22] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 14/22] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/19
- [PATCH v7 15/22] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/19
- [PATCH v7 16/22] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 17/22] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2022/01/19
- [PATCH v7 18/22] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2022/01/19
- [PATCH v7 19/22] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2022/01/19
- [PATCH v7 20/22] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2022/01/19
- [PATCH v7 21/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/19
- Re: [PATCH v7 21/22] target/riscv: Enable uxl field write,
Alistair Francis <=
- Re: [PATCH v7 21/22] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/19
[PATCH v7 22/22] target/riscv: Relax UXL field for debugging, LIU Zhiwei, 2022/01/19