Re: [PATCH v7 21/22] target/riscv: Enable uxl field write

[LIU Zhiwei]

On 2022/1/20 上午8:35, Alistair Francis wrote:
> On Wed, Jan 19, 2022 at 3:34 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
> > Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >   target/riscv/csr.c | 17 ++++++++++++-----
> >   1 file changed, 12 insertions(+), 5 deletions(-)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index b11d92b51b..90f78eca65 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -572,6 +572,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int 
> > csrno,
> >   {
> >       uint64_t mstatus = env->mstatus;
> >       uint64_t mask = 0;
> > +    RISCVMXL xl = riscv_cpu_mxl(env);
> >
> >       /* flush tlb on mstatus fields that affect VM */
> >       if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
> > @@ -583,21 +584,22 @@ static RISCVException write_mstatus(CPURISCVState *env, 
> > int csrno,
> >           MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
> >           MSTATUS_TW | MSTATUS_VS;
> >
> > -    if (riscv_cpu_mxl(env) != MXL_RV32) {
> > +    if (xl != MXL_RV32) {
> >           /*
> >            * RV32: MPV and GVA are not in mstatus. The current plan is to
> >            * add them to mstatush. For now, we just don't support it.
> >            */
> >           mask |= MSTATUS_MPV | MSTATUS_GVA;
> > +        if ((val & MSTATUS64_UXL) != 0) {
> > +            mask |= MSTATUS64_UXL;
> > +        }
> >       }
> >
> >       mstatus = (mstatus & ~mask) | (val & mask);
> >
> > -    RISCVMXL xl = riscv_cpu_mxl(env);
> >       if (xl > MXL_RV32) {
> > -        /* SXL and UXL fields are for now read only */
> > +        /* SXL field is for now read only */
> >           mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
> > -        mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
> This change causes:
>
> ERROR:../target/riscv/translate.c:295:get_gpr: code should not be reached
>
> to assert when running an Xvisor (Hypervisor extension) guest on the
> 64-bit virt machine.

Hi Alistair,

Thanks for pointing it out. I will have a test on Xvisor.

Thanks,
Zhiwei

> Alistair