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[PATCH v8 22/23] target/riscv: Enable uxl field write
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From: |
LIU Zhiwei |
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Subject: |
[PATCH v8 22/23] target/riscv: Enable uxl field write |
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Date: |
Thu, 20 Jan 2022 20:20:49 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 3 +++
target/riscv/csr.c | 28 ++++++++++++++++++++++------
2 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 5a6d49aa64..7c87433645 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -449,6 +449,9 @@ typedef enum {
#define COUNTEREN_IR (1 << 2)
#define COUNTEREN_HPM3 (1 << 3)
+/* vsstatus CSR bits */
+#define VSSTATUS64_UXL 0x0000000300000000ULL
+
/* Privilege modes */
#define PRV_U 0
#define PRV_S 1
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index b11d92b51b..523d07a95e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -496,7 +496,7 @@ static const target_ulong vs_delegable_excps =
DELEGABLE_EXCPS &
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
- SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL;
+ SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
static const target_ulong hip_writable_mask = MIP_VSSIP;
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
MIP_VSEIP;
@@ -572,6 +572,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int
csrno,
{
uint64_t mstatus = env->mstatus;
uint64_t mask = 0;
+ RISCVMXL xl = riscv_cpu_mxl(env);
/* flush tlb on mstatus fields that affect VM */
if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
@@ -583,21 +584,22 @@ static RISCVException write_mstatus(CPURISCVState *env,
int csrno,
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW | MSTATUS_VS;
- if (riscv_cpu_mxl(env) != MXL_RV32) {
+ if (xl != MXL_RV32) {
/*
* RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
*/
mask |= MSTATUS_MPV | MSTATUS_GVA;
+ if ((val & MSTATUS64_UXL) != 0) {
+ mask |= MSTATUS64_UXL;
+ }
}
mstatus = (mstatus & ~mask) | (val & mask);
- RISCVMXL xl = riscv_cpu_mxl(env);
if (xl > MXL_RV32) {
- /* SXL and UXL fields are for now read only */
+ /* SXL field is for now read only */
mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
- mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
}
env->mstatus = mstatus;
env->xl = cpu_recompute_xl(env);
@@ -898,6 +900,9 @@ static RISCVException read_sstatus_i128(CPURISCVState *env,
int csrno,
{
uint64_t mask = sstatus_v1_10_mask;
uint64_t sstatus = env->mstatus & mask;
+ if (env->xl != MXL_RV32) {
+ mask |= SSTATUS64_UXL;
+ }
*val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
return RISCV_EXCP_NONE;
@@ -907,7 +912,9 @@ static RISCVException read_sstatus(CPURISCVState *env, int
csrno,
target_ulong *val)
{
target_ulong mask = (sstatus_v1_10_mask);
-
+ if (env->xl != MXL_RV32) {
+ mask |= SSTATUS64_UXL;
+ }
/* TODO: Use SXL not MXL. */
*val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
return RISCV_EXCP_NONE;
@@ -917,6 +924,12 @@ static RISCVException write_sstatus(CPURISCVState *env,
int csrno,
target_ulong val)
{
target_ulong mask = (sstatus_v1_10_mask);
+
+ if (env->xl != MXL_RV32) {
+ if ((val & SSTATUS64_UXL) != 0) {
+ mask |= SSTATUS64_UXL;
+ }
+ }
target_ulong newval = (env->mstatus & ~mask) | (val & mask);
return write_mstatus(env, CSR_MSTATUS, newval);
}
@@ -1380,6 +1393,9 @@ static RISCVException write_vsstatus(CPURISCVState *env,
int csrno,
target_ulong val)
{
uint64_t mask = (target_ulong)-1;
+ if ((val & VSSTATUS64_UXL) == 0) {
+ mask &= ~VSSTATUS64_UXL;
+ }
env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
return RISCV_EXCP_NONE;
}
--
2.25.1
- [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base], (continued)
- [PATCH v8 12/23] target/riscv: Alloc tcg global for cur_pm[mask|base], LIU Zhiwei, 2022/01/20
- [PATCH v8 11/23] target/riscv: Create current pm fields in env, LIU Zhiwei, 2022/01/20
- [PATCH v8 13/23] target/riscv: Calculate address according to XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/20
- [PATCH v8 15/23] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/20
- [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2022/01/20
- [PATCH v8 18/23] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2022/01/20
- [PATCH v8 19/23] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2022/01/20
- [PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 22/23] target/riscv: Enable uxl field write,
LIU Zhiwei <=
- [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor, LIU Zhiwei, 2022/01/20
- [PATCH v8 23/23] target/riscv: Relax UXL field for debugging, LIU Zhiwei, 2022/01/20
- Re: [PATCH v8 00/23] Support UXL filed in xstatus, Alistair Francis, 2022/01/20