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[PATCH v8 23/23] target/riscv: Relax UXL field for debugging
From: |
LIU Zhiwei |
Subject: |
[PATCH v8 23/23] target/riscv: Relax UXL field for debugging |
Date: |
Thu, 20 Jan 2022 20:20:50 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 523d07a95e..e5f9d4ef93 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -584,7 +584,7 @@ static RISCVException write_mstatus(CPURISCVState *env, int
csrno,
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW | MSTATUS_VS;
- if (xl != MXL_RV32) {
+ if (xl != MXL_RV32 || env->debugger) {
/*
* RV32: MPV and GVA are not in mstatus. The current plan is to
* add them to mstatush. For now, we just don't support it.
@@ -900,7 +900,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env,
int csrno,
{
uint64_t mask = sstatus_v1_10_mask;
uint64_t sstatus = env->mstatus & mask;
- if (env->xl != MXL_RV32) {
+ if (env->xl != MXL_RV32 || env->debugger) {
mask |= SSTATUS64_UXL;
}
@@ -912,7 +912,7 @@ static RISCVException read_sstatus(CPURISCVState *env, int
csrno,
target_ulong *val)
{
target_ulong mask = (sstatus_v1_10_mask);
- if (env->xl != MXL_RV32) {
+ if (env->xl != MXL_RV32 || env->debugger) {
mask |= SSTATUS64_UXL;
}
/* TODO: Use SXL not MXL. */
@@ -925,7 +925,7 @@ static RISCVException write_sstatus(CPURISCVState *env, int
csrno,
{
target_ulong mask = (sstatus_v1_10_mask);
- if (env->xl != MXL_RV32) {
+ if (env->xl != MXL_RV32 || env->debugger) {
if ((val & SSTATUS64_UXL) != 0) {
mask |= SSTATUS64_UXL;
}
--
2.25.1
- [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base, (continued)
- [PATCH v8 14/23] target/riscv: Split pm_enabled into mask and base, LIU Zhiwei, 2022/01/20
- [PATCH v8 15/23] target/riscv: Split out the vill from vtype, LIU Zhiwei, 2022/01/20
- [PATCH v8 16/23] target/riscv: Adjust vsetvl according to XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 17/23] target/riscv: Remove VILL field in VTYPE, LIU Zhiwei, 2022/01/20
- [PATCH v8 18/23] target/riscv: Fix check range for first fault only, LIU Zhiwei, 2022/01/20
- [PATCH v8 19/23] target/riscv: Adjust vector address with mask, LIU Zhiwei, 2022/01/20
- [PATCH v8 20/23] target/riscv: Adjust scalar reg in vector with XLEN, LIU Zhiwei, 2022/01/20
- [PATCH v8 22/23] target/riscv: Enable uxl field write, LIU Zhiwei, 2022/01/20
- [PATCH v8 21/23] target/riscv: Set default XLEN for hypervisor, LIU Zhiwei, 2022/01/20
- [PATCH v8 23/23] target/riscv: Relax UXL field for debugging,
LIU Zhiwei <=
- Re: [PATCH v8 00/23] Support UXL filed in xstatus, Alistair Francis, 2022/01/20