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Re: [PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12


From: Alistair Francis
Subject: Re: [PATCH v3 6/6] target/riscv: Enable privileged spec version 1.12
Date: Tue, 22 Feb 2022 07:40:29 +1000

On Sun, Feb 6, 2022 at 7:51 PM Atish Patra <atishp@rivosinc.com> wrote:
>
> Virt machine uses privileged specification version 1.12 now.
> All other machine continue to use the default one defined for that
> machine unless changed to 1.12 by the user explicitly.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 8 +++++---
>  target/riscv/csr.c | 5 +++++
>  2 files changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2668f9c358b2..1c72dfffdc61 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -150,7 +150,7 @@ static void riscv_any_cpu_init(Object *obj)
>  #elif defined(TARGET_RISCV64)
>      set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
>  #endif
> -    set_priv_version(env, PRIV_VERSION_1_11_0);
> +    set_priv_version(env, PRIV_VERSION_1_12_0);
>  }
>
>  #if defined(TARGET_RISCV64)
> @@ -474,7 +474,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>      }
>
>      if (cpu->cfg.priv_spec) {
> -        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
> +        if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
> +            priv_version = PRIV_VERSION_1_12_0;
> +        } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
>              priv_version = PRIV_VERSION_1_11_0;
>          } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
>              priv_version = PRIV_VERSION_1_10_0;
> @@ -489,7 +491,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error 
> **errp)
>      if (priv_version) {
>          set_priv_version(env, priv_version);
>      } else if (!env->priv_ver) {
> -        set_priv_version(env, PRIV_VERSION_1_11_0);
> +        set_priv_version(env, PRIV_VERSION_1_12_0);
>      }
>
>      if (cpu->cfg.mmu) {
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index ff7e36596447..1c70c19cf9bd 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2886,6 +2886,7 @@ static inline RISCVException 
> riscv_csrrw_check(CPURISCVState *env,
>  {
>      /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
>      int read_only = get_field(csrno, 0xC00) == 3;
> +    int csr_min_priv = csr_ops[csrno].min_priv_ver;
>  #if !defined(CONFIG_USER_ONLY)
>      int effective_priv = env->priv;
>
> @@ -2918,6 +2919,10 @@ static inline RISCVException 
> riscv_csrrw_check(CPURISCVState *env,
>          return RISCV_EXCP_ILLEGAL_INST;
>      }
>
> +    if (env->priv_ver < csr_min_priv) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
> +
>      return csr_ops[csrno].predicate(env, csrno);
>  }
>
> --
> 2.30.2
>
>



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